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[RISCV] Implement MC support for Zvfbfa extension
This patch adds MC support for Zvfbfa https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc Since Zvfbfa implies Zve32f, vector floating-point instructions can be used directly with Zvfbfa extension.
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18 files changed

+154
-20
lines changed

18 files changed

+154
-20
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,7 @@
215215
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
216216
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
217217
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
218+
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
218219
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
219220
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
220221
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)

‎clang/test/Preprocessor/riscv-target-features.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,7 @@
177177
// CHECK-NOT: __riscv_zicfiss {{.*$}}
178178
// CHECK-NOT: __riscv_ztso {{.*$}}
179179
// CHECK-NOT: __riscv_zvbc32e {{.*$}}
180+
// CHECK-NOT: __riscv_zvfbfa {{.*$}}
180181
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
181182
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
182183
// CHECK-NOT: __riscv_zvkgs {{.*$}}
@@ -1551,6 +1552,14 @@
15511552
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
15521553
// CHECK-ZTSO-EXT: __riscv_ztso 1000000{{$}}
15531554

1555+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1556+
// RUN: -march=rv32ifzvfbfa0p1 -E -dM %s \
1557+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s
1558+
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1559+
// RUN: -march=rv64ifzvfbfa0p1 -E -dM %s \
1560+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s
1561+
// CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}}
1562+
15541563
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
15551564
// RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
15561565
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s

‎llvm/docs/RISCVUsage.rst‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -231,6 +231,7 @@ on support follow.
231231
``Zve64x`` Supported
232232
``Zve64f`` Supported
233233
``Zve64d`` Supported
234+
``Zvfbfa`` Assembly Support
234235
``Zvfbfmin`` Supported
235236
``Zvfbfwma`` Supported
236237
``Zvfh`` Supported

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,7 @@ Changes to the RISC-V Backend
119119
and data using mapping symbols such as `$x` and `$d`. Switching architectures
120120
using `$x` with an architecture string suffix is not yet supported.
121121
* Ssctr and Smctr extensions are no longer experimental.
122+
* Add support for Zvfbfa (Additional BF16 vector compute support)
122123

123124
Changes to the WebAssembly Backend
124125
----------------------------------

‎llvm/include/llvm/TargetParser/RISCVTargetParser.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
9898
}
9999

100100
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
101-
bool MaskAgnostic);
101+
bool MaskAgnostic, bool Altfmt = false);
102102

103103
LLVM_ABI unsigned encodeXSfmmVType(unsigned SEW, unsigned Widen, bool AltFmt);
104104

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 21 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
121121

122122
bool parseVTypeToken(const AsmToken &Tok, VTypeState &State, unsigned &Sew,
123123
unsigned &Lmul, bool &Fractional, bool &TailAgnostic,
124-
bool &MaskAgnostic);
124+
bool &MaskAgnostic, bool &AltFmt);
125125
bool generateVTypeError(SMLoc ErrorLoc);
126126

127127
bool generateXSfmmVTypeError(SMLoc ErrorLoc);
@@ -2261,14 +2261,23 @@ ParseStatus RISCVAsmParser::parseJALOffset(OperandVector &Operands) {
22612261
bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State,
22622262
unsigned &Sew, unsigned &Lmul,
22632263
bool &Fractional, bool &TailAgnostic,
2264-
bool &MaskAgnostic) {
2264+
bool &MaskAgnostic, bool &AltFmt) {
22652265
if (Tok.isNot(AsmToken::Identifier))
22662266
return true;
22672267

22682268
StringRef Identifier = Tok.getIdentifier();
22692269
if (State < VTypeState::SeenSew && Identifier.consume_front("e")) {
2270-
if (Identifier.getAsInteger(10, Sew))
2271-
return true;
2270+
if (Identifier.getAsInteger(10, Sew)) {
2271+
if (Identifier == "16alt") {
2272+
AltFmt = true;
2273+
Sew = 16;
2274+
} else if (Identifier == "8alt") {
2275+
AltFmt = true;
2276+
Sew = 8;
2277+
} else {
2278+
return true;
2279+
}
2280+
}
22722281
if (!RISCVVType::isValidSEW(Sew))
22732282
return true;
22742283

@@ -2340,11 +2349,12 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
23402349
bool Fractional = false;
23412350
bool TailAgnostic = false;
23422351
bool MaskAgnostic = false;
2352+
bool AltFmt = false;
23432353

23442354
VTypeState State = VTypeState::SeenNothingYet;
23452355
do {
23462356
if (parseVTypeToken(getTok(), State, Sew, Lmul, Fractional, TailAgnostic,
2347-
MaskAgnostic)) {
2357+
MaskAgnostic, AltFmt)) {
23482358
// The first time, errors return NoMatch rather than Failure
23492359
if (State == VTypeState::SeenNothingYet)
23502360
return ParseStatus::NoMatch;
@@ -2370,12 +2380,17 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
23702380
}
23712381

23722382
unsigned VTypeI =
2373-
RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic);
2383+
RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic, AltFmt);
23742384
Operands.push_back(RISCVOperand::createVType(VTypeI, S));
23752385
return ParseStatus::Success;
23762386
}
23772387

23782388
bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
2389+
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa))
2390+
return Error(
2391+
ErrorLoc,
2392+
"operand must be "
2393+
"e[8|8alt|16|16alt|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
23792394
return Error(
23802395
ErrorLoc,
23812396
"operand must be "

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -216,9 +216,12 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
216216
const MCSubtargetInfo &STI, raw_ostream &O) {
217217
unsigned Imm = MI->getOperand(OpNo).getImm();
218218
// Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
219-
// or non-zero in bits 8 and above.
219+
// , altfmt=1 without zvfbaf extension, or non-zero in bits 9 and above.
220220
if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
221-
RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) {
221+
RISCVVType::getSEW(Imm) > 64 ||
222+
(RISCVVType::isAltFmt(Imm) &&
223+
!STI.hasFeature(RISCV::FeatureStdExtZvfbfa)) ||
224+
(Imm >> 9) != 0) {
222225
O << formatImm(Imm);
223226
return;
224227
}

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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Original file line numberDiff line numberDiff line change
@@ -680,19 +680,38 @@ def FeatureStdExtV
680680
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>,
681681
RISCVExtensionBitmask<0, 21>;
682682

683+
def FeatureStdExtZvfbfa
684+
: RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",
685+
[FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
686+
def HasStdExtZvfbfa : Predicate<"Subtarget->hasStdExtZvfbfa()">,
687+
AssemblerPredicate<(all_of FeatureStdExtZvfbfa),
688+
"'Zvfbfa' (Additional BF16 vector compute support)">;
689+
683690
def FeatureStdExtZvfbfmin
684691
: RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>;
685692
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
686693
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
687694
"'Zvfbfmin' (Vector BF16 Converts)">;
688695

696+
def HasStdExtZvfbfminOrZvfbfa
697+
: Predicate<"Subtarget->hasStdExtZvfbfmin() || Subtarget->hasStdExtZvfbfa()">,
698+
AssemblerPredicate<(any_of FeatureStdExtZvfbfmin, FeatureStdExtZvfbfa),
699+
"'Zvfbfmin' (Vector BF16 Converts) or "
700+
"'Zvfbfa' (Additional BF16 vector compute support)">;
701+
689702
def FeatureStdExtZvfbfwma
690703
: RISCVExtension<1, 0, "Vector BF16 widening mul-add",
691704
[FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
692705
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
693706
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
694707
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
695708

709+
def HasStdExtZvfbfwmaOrZvfbfa
710+
: Predicate<"Subtarget->hasStdExtZvfbfwma() || Subtarget->hasStdExtZvfbfa()">,
711+
AssemblerPredicate<(any_of FeatureStdExtZvfbfwma, FeatureStdExtZvfbfa),
712+
"'Zvfbfwma' (Vector BF16 widening mul-add) or "
713+
"'Zvfbfa' (Additional BF16 vector compute support)">;
714+
696715
def FeatureStdExtZvfhmin
697716
: RISCVExtension<1, 0,
698717
"Vector Half-Precision Floating-Point Minimal",

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,15 +17,15 @@
1717
// Instructions
1818
//===----------------------------------------------------------------------===//
1919

20-
let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd",
20+
let Predicates = [HasStdExtZvfbfminOrZvfbfa], Constraints = "@earlyclobber $vd",
2121
mayRaiseFPException = true in {
2222
let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in
2323
defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>;
2424
let Uses = [FRM, VL, VTYPE] in
2525
defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>;
2626
}
2727

28-
let Predicates = [HasStdExtZvfbfwma],
28+
let Predicates = [HasStdExtZvfbfwmaOrZvfbfa],
2929
Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb",
3030
RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFPException = true,
3131
DestEEW = EEWSEWx2 in {

‎llvm/lib/TargetParser/RISCVTargetParser.cpp‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -153,12 +153,13 @@ namespace RISCVVType {
153153
//
154154
// Bits | Name | Description
155155
// -----+------------+------------------------------------------------
156+
// 8 | altfmt | Alternative format for bf16
156157
// 7 | vma | Vector mask agnostic
157158
// 6 | vta | Vector tail agnostic
158159
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
159160
// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
160161
unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic,
161-
bool MaskAgnostic) {
162+
bool MaskAgnostic, bool Altfmt) {
162163
assert(isValidSEW(SEW) && "Invalid SEW");
163164
unsigned VLMulBits = static_cast<unsigned>(VLMul);
164165
unsigned VSEWBits = encodeSEW(SEW);
@@ -167,6 +168,8 @@ unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic,
167168
VTypeI |= 0x40;
168169
if (MaskAgnostic)
169170
VTypeI |= 0x80;
171+
if (Altfmt)
172+
VTypeI |= 0x100;
170173

171174
return VTypeI;
172175
}
@@ -200,6 +203,10 @@ void printVType(unsigned VType, raw_ostream &OS) {
200203
unsigned Sew = getSEW(VType);
201204
OS << "e" << Sew;
202205

206+
bool AltFmt = RISCVVType::isAltFmt(VType);
207+
if (AltFmt)
208+
OS << "alt";
209+
203210
unsigned LMul;
204211
bool Fractional;
205212
std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));

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