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Revert "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have …"
This reverts commit e4f2191.
1 parent 0439a4e commit eb8fc8e

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5 files changed

+2
-150
lines changed

5 files changed

+2
-150
lines changed

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1854,10 +1854,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18541854
if (Subtarget->is64Bit()) {
18551855
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
18561856
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1857-
setOperationAction(ISD::MULHU, MVT::i64,
1858-
Subtarget->isVIS3() ? Legal : Expand);
1859-
setOperationAction(ISD::MULHS, MVT::i64,
1860-
Subtarget->isVIS3() ? Legal : Expand);
1857+
setOperationAction(ISD::MULHU, MVT::i64, Expand);
1858+
setOperationAction(ISD::MULHS, MVT::i64, Expand);
18611859

18621860
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
18631861
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);

‎llvm/lib/Target/Sparc/SparcInstrVIS.td‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -294,14 +294,4 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
294294
// VIS3 instruction patterns.
295295
let Predicates = [HasVIS3] in {
296296
def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
297-
298-
def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>;
299-
// Signed "MULXHI".
300-
// Based on the formula presented in OSA2011 §7.140, but with bitops to select
301-
// the values to be added.
302-
// TODO: This expansion should probably be moved to DAG legalization phase.
303-
def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
304-
(SUBrr (UMULXHI $lhs, $rhs),
305-
(ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
306-
(ANDrr (SRAXri $rhs, 63), $lhs)))>;
307297
} // Predicates = [HasVIS3]

‎llvm/test/CodeGen/SPARC/multiply-extension.ll‎

Lines changed: 0 additions & 59 deletions
This file was deleted.

‎llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll‎

Lines changed: 0 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
33
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
4-
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu -mattr=vis3 | FileCheck %s --check-prefixes=SPARC64-VIS3
54

65
define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
76
; SPARC-LABEL: muloti_test:
@@ -214,49 +213,6 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
214213
; SPARC64-NEXT: srl %i3, 0, %i2
215214
; SPARC64-NEXT: ret
216215
; SPARC64-NEXT: restore
217-
;
218-
; SPARC64-VIS3-LABEL: muloti_test:
219-
; SPARC64-VIS3: .register %g2, #scratch
220-
; SPARC64-VIS3-NEXT: .register %g3, #scratch
221-
; SPARC64-VIS3-NEXT: ! %bb.0: ! %start
222-
; SPARC64-VIS3-NEXT: save %sp, -128, %sp
223-
; SPARC64-VIS3-NEXT: mov %g0, %i5
224-
; SPARC64-VIS3-NEXT: umulxhi %i0, %i3, %i4
225-
; SPARC64-VIS3-NEXT: srax %i0, 63, %g2
226-
; SPARC64-VIS3-NEXT: mulx %g2, %i3, %g3
227-
; SPARC64-VIS3-NEXT: add %i4, %g3, %i4
228-
; SPARC64-VIS3-NEXT: umulxhi %i1, %i3, %g3
229-
; SPARC64-VIS3-NEXT: mulx %i0, %i3, %g4
230-
; SPARC64-VIS3-NEXT: addcc %g4, %g3, %g3
231-
; SPARC64-VIS3-NEXT: addxccc %i4, %g0, %g4
232-
; SPARC64-VIS3-NEXT: umulxhi %i1, %i2, %i4
233-
; SPARC64-VIS3-NEXT: srax %i2, 63, %g5
234-
; SPARC64-VIS3-NEXT: mulx %i1, %g5, %l0
235-
; SPARC64-VIS3-NEXT: add %i4, %l0, %l0
236-
; SPARC64-VIS3-NEXT: mulx %i1, %i2, %i4
237-
; SPARC64-VIS3-NEXT: addcc %i4, %g3, %i4
238-
; SPARC64-VIS3-NEXT: addxccc %l0, %g0, %g3
239-
; SPARC64-VIS3-NEXT: srax %g3, 63, %l0
240-
; SPARC64-VIS3-NEXT: addcc %g4, %g3, %g3
241-
; SPARC64-VIS3-NEXT: srax %g4, 63, %g4
242-
; SPARC64-VIS3-NEXT: addxccc %g4, %l0, %g4
243-
; SPARC64-VIS3-NEXT: and %g5, %i0, %g5
244-
; SPARC64-VIS3-NEXT: and %g2, %i2, %g2
245-
; SPARC64-VIS3-NEXT: add %g2, %g5, %g2
246-
; SPARC64-VIS3-NEXT: umulxhi %i0, %i2, %g5
247-
; SPARC64-VIS3-NEXT: sub %g5, %g2, %g2
248-
; SPARC64-VIS3-NEXT: mulx %i0, %i2, %i0
249-
; SPARC64-VIS3-NEXT: addcc %i0, %g3, %i0
250-
; SPARC64-VIS3-NEXT: addxccc %g2, %g4, %i2
251-
; SPARC64-VIS3-NEXT: srax %i4, 63, %g2
252-
; SPARC64-VIS3-NEXT: xor %i2, %g2, %i2
253-
; SPARC64-VIS3-NEXT: xor %i0, %g2, %i0
254-
; SPARC64-VIS3-NEXT: or %i0, %i2, %i0
255-
; SPARC64-VIS3-NEXT: movrnz %i0, 1, %i5
256-
; SPARC64-VIS3-NEXT: mulx %i1, %i3, %i1
257-
; SPARC64-VIS3-NEXT: srl %i5, 0, %i2
258-
; SPARC64-VIS3-NEXT: ret
259-
; SPARC64-VIS3-NEXT: restore %g0, %i4, %o0
260216
start:
261217
%0 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %l, i128 %r)
262218
%1 = extractvalue { i128, i1 } %0, 0

‎llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll‎

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
33
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
4-
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu -mattr=vis3 | FileCheck %s --check-prefixes=SPARC64-VIS3
54

65
define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
76
; SPARC-LABEL: muloti_test:
@@ -200,38 +199,6 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
200199
; SPARC64-NEXT: srl %i1, 0, %i2
201200
; SPARC64-NEXT: ret
202201
; SPARC64-NEXT: restore %g0, %o1, %o1
203-
;
204-
; SPARC64-VIS3-LABEL: muloti_test:
205-
; SPARC64-VIS3: .register %g2, #scratch
206-
; SPARC64-VIS3-NEXT: .register %g3, #scratch
207-
; SPARC64-VIS3-NEXT: ! %bb.0: ! %start
208-
; SPARC64-VIS3-NEXT: save %sp, -128, %sp
209-
; SPARC64-VIS3-NEXT: mov %g0, %i5
210-
; SPARC64-VIS3-NEXT: mov %g0, %g2
211-
; SPARC64-VIS3-NEXT: mov %g0, %g3
212-
; SPARC64-VIS3-NEXT: mov %g0, %g4
213-
; SPARC64-VIS3-NEXT: mov %g0, %g5
214-
; SPARC64-VIS3-NEXT: mulx %i2, %i1, %i4
215-
; SPARC64-VIS3-NEXT: mulx %i0, %i3, %l0
216-
; SPARC64-VIS3-NEXT: add %l0, %i4, %i4
217-
; SPARC64-VIS3-NEXT: umulxhi %i1, %i3, %l0
218-
; SPARC64-VIS3-NEXT: add %l0, %i4, %i4
219-
; SPARC64-VIS3-NEXT: cmp %i4, %l0
220-
; SPARC64-VIS3-NEXT: movrnz %i2, 1, %g2
221-
; SPARC64-VIS3-NEXT: movrnz %i0, 1, %g3
222-
; SPARC64-VIS3-NEXT: and %g3, %g2, %g2
223-
; SPARC64-VIS3-NEXT: umulxhi %i0, %i3, %i0
224-
; SPARC64-VIS3-NEXT: movrnz %i0, 1, %g4
225-
; SPARC64-VIS3-NEXT: movcs %xcc, 1, %i5
226-
; SPARC64-VIS3-NEXT: or %g2, %g4, %i0
227-
; SPARC64-VIS3-NEXT: umulxhi %i2, %i1, %i2
228-
; SPARC64-VIS3-NEXT: movrnz %i2, 1, %g5
229-
; SPARC64-VIS3-NEXT: or %i0, %g5, %i0
230-
; SPARC64-VIS3-NEXT: or %i0, %i5, %i0
231-
; SPARC64-VIS3-NEXT: mulx %i1, %i3, %i1
232-
; SPARC64-VIS3-NEXT: srl %i0, 0, %i2
233-
; SPARC64-VIS3-NEXT: ret
234-
; SPARC64-VIS3-NEXT: restore %g0, %i4, %o0
235202
start:
236203
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r)
237204
%1 = extractvalue { i128, i1 } %0, 0

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