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alexrpalexrp
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[llvm][SystemZ] Fix parsing of .cfi_undefined with percent-less registers. (#107032)
This is just e3d658b applied to SystemZ. An example of this being used in the wild: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/s390/s390-64/start.S;h=59eeb7e998227bdf32029cd074f0876c450404ea;hb=HEAD#l63
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-26
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3 files changed

+161
-26
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‎llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp‎

Lines changed: 33 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -416,7 +416,8 @@ class SystemZAsmParser : public MCTargetAsmParser {
416416
return static_cast<SystemZTargetStreamer &>(TS);
417417
}
418418

419-
bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
419+
bool parseRegister(Register &Reg, bool RequirePercent,
420+
bool RestoreOnFailure = false);
420421

421422
bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
422423

@@ -495,7 +496,7 @@ class SystemZAsmParser : public MCTargetAsmParser {
495496
ParseStatus parseDirective(AsmToken DirectiveID) override;
496497
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
497498
bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
498-
bool RestoreOnFailure);
499+
bool RequirePercent, bool RestoreOnFailure);
499500
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
500501
SMLoc &EndLoc) override;
501502
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -756,34 +757,40 @@ void SystemZOperand::print(raw_ostream &OS) const {
756757
}
757758

758759
// Parse one register of the form %<prefix><number>.
759-
bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
760-
Reg.StartLoc = Parser.getTok().getLoc();
761-
762-
// Eat the % prefix.
763-
if (Parser.getTok().isNot(AsmToken::Percent))
764-
return Error(Parser.getTok().getLoc(), "register expected");
760+
bool SystemZAsmParser::parseRegister(Register &Reg, bool RequirePercent,
761+
bool RestoreOnFailure) {
765762
const AsmToken &PercentTok = Parser.getTok();
766-
Parser.Lex();
763+
bool HasPercent = PercentTok.is(AsmToken::Percent);
764+
765+
Reg.StartLoc = PercentTok.getLoc();
766+
767+
if (RequirePercent && PercentTok.isNot(AsmToken::Percent))
768+
return Error(PercentTok.getLoc(), "register expected");
769+
770+
if (HasPercent) {
771+
Parser.Lex(); // Eat percent token.
772+
}
767773

768774
// Expect a register name.
769775
if (Parser.getTok().isNot(AsmToken::Identifier)) {
770-
if (RestoreOnFailure)
776+
if (RestoreOnFailure && HasPercent)
771777
getLexer().UnLex(PercentTok);
772-
return Error(Reg.StartLoc, "invalid register");
778+
return Error(Reg.StartLoc,
779+
HasPercent ? "invalid register" : "register expected");
773780
}
774781

775782
// Check that there's a prefix.
776783
StringRef Name = Parser.getTok().getString();
777784
if (Name.size() < 2) {
778-
if (RestoreOnFailure)
785+
if (RestoreOnFailure && HasPercent)
779786
getLexer().UnLex(PercentTok);
780787
return Error(Reg.StartLoc, "invalid register");
781788
}
782789
char Prefix = Name[0];
783790

784791
// Treat the rest of the register name as a register number.
785792
if (Name.substr(1).getAsInteger(10, Reg.Num)) {
786-
if (RestoreOnFailure)
793+
if (RestoreOnFailure && HasPercent)
787794
getLexer().UnLex(PercentTok);
788795
return Error(Reg.StartLoc, "invalid register");
789796
}
@@ -800,7 +807,7 @@ bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
800807
else if (Prefix == 'c' && Reg.Num < 16)
801808
Reg.Group = RegCR;
802809
else {
803-
if (RestoreOnFailure)
810+
if (RestoreOnFailure && HasPercent)
804811
getLexer().UnLex(PercentTok);
805812
return Error(Reg.StartLoc, "invalid register");
806813
}
@@ -842,7 +849,7 @@ ParseStatus SystemZAsmParser::parseRegister(OperandVector &Operands,
842849

843850
// Handle register names of the form %<prefix><number>
844851
if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
845-
if (parseRegister(Reg))
852+
if (parseRegister(Reg, /*RequirePercent=*/true))
846853
return ParseStatus::Failure;
847854

848855
// Check the parsed register group "Reg.Group" with the expected "Group"
@@ -918,7 +925,7 @@ ParseStatus SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
918925
return ParseStatus::NoMatch;
919926

920927
Register Reg;
921-
if (parseRegister(Reg))
928+
if (parseRegister(Reg, /*RequirePercent=*/true))
922929
return ParseStatus::Failure;
923930

924931
if (Reg.Num > 15)
@@ -1025,7 +1032,7 @@ bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
10251032
if (isParsingATT() && getLexer().is(AsmToken::Percent)) {
10261033
// Parse the first register.
10271034
HaveReg1 = true;
1028-
if (parseRegister(Reg1))
1035+
if (parseRegister(Reg1, /*RequirePercent=*/true))
10291036
return true;
10301037
}
10311038
// So if we have an integer as the first token in ([tok1], ..), it could:
@@ -1065,7 +1072,7 @@ bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
10651072
if (parseIntegerRegister(Reg2, RegGR))
10661073
return true;
10671074
} else {
1068-
if (isParsingATT() && parseRegister(Reg2))
1075+
if (isParsingATT() && parseRegister(Reg2, /*RequirePercent=*/true))
10691076
return true;
10701077
}
10711078
}
@@ -1355,9 +1362,10 @@ bool SystemZAsmParser::ParseGNUAttribute(SMLoc L) {
13551362
}
13561363

13571364
bool SystemZAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1358-
SMLoc &EndLoc, bool RestoreOnFailure) {
1365+
SMLoc &EndLoc, bool RequirePercent,
1366+
bool RestoreOnFailure) {
13591367
Register Reg;
1360-
if (parseRegister(Reg, RestoreOnFailure))
1368+
if (parseRegister(Reg, RequirePercent, RestoreOnFailure))
13611369
return true;
13621370
if (Reg.Group == RegGR)
13631371
RegNo = SystemZMC::GR64Regs[Reg.Num];
@@ -1376,12 +1384,14 @@ bool SystemZAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
13761384

13771385
bool SystemZAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
13781386
SMLoc &EndLoc) {
1379-
return ParseRegister(Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1387+
return ParseRegister(Reg, StartLoc, EndLoc, /*RequirePercent=*/false,
1388+
/*RestoreOnFailure=*/false);
13801389
}
13811390

13821391
ParseStatus SystemZAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
13831392
SMLoc &EndLoc) {
1384-
bool Result = ParseRegister(Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1393+
bool Result = ParseRegister(Reg, StartLoc, EndLoc, /*RequirePercent=*/false,
1394+
/*RestoreOnFailure=*/true);
13851395
bool PendingErrors = getParser().hasPendingError();
13861396
getParser().clearPendingErrors();
13871397
if (PendingErrors)
@@ -1482,7 +1492,7 @@ bool SystemZAsmParser::parseOperand(OperandVector &Operands,
14821492
// the instruction isn't recognized.
14831493
if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
14841494
Register Reg;
1485-
if (parseRegister(Reg))
1495+
if (parseRegister(Reg, /*RequirePercent=*/true))
14861496
return true;
14871497
Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
14881498
return false;

‎llvm/test/MC/SystemZ/regs-bad.s‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -262,8 +262,6 @@
262262

263263
# Test general register parsing, with no predetermined class in mind.
264264
#
265-
#CHECK: error: register expected
266-
#CHECK: .cfi_offset r0,0
267265
#CHECK: error: invalid register
268266
#CHECK: .cfi_offset %,0
269267
#CHECK: error: invalid register
@@ -289,7 +287,6 @@
289287
#CHECK: error: invalid register
290288
#CHECK: .cfi_offset %arid,0
291289

292-
.cfi_offset r0,0
293290
.cfi_offset %,0
294291
.cfi_offset %r,0
295292
.cfi_offset %f,0

‎llvm/test/MC/SystemZ/regs-good.s‎

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,70 @@
176176
st 0, 4095(1,15)
177177
st 0, 4095(15,1)
178178

179+
#CHECK: .cfi_offset %r0, 0
180+
#CHECK: .cfi_offset %r1, 8
181+
#CHECK: .cfi_offset %r2, 16
182+
#CHECK: .cfi_offset %r3, 24
183+
#CHECK: .cfi_offset %r4, 32
184+
#CHECK: .cfi_offset %r5, 40
185+
#CHECK: .cfi_offset %r6, 48
186+
#CHECK: .cfi_offset %r7, 56
187+
#CHECK: .cfi_offset %r8, 64
188+
#CHECK: .cfi_offset %r9, 72
189+
#CHECK: .cfi_offset %r10, 80
190+
#CHECK: .cfi_offset %r11, 88
191+
#CHECK: .cfi_offset %r12, 96
192+
#CHECK: .cfi_offset %r13, 104
193+
#CHECK: .cfi_offset %r14, 112
194+
#CHECK: .cfi_offset %r15, 120
195+
#CHECK: .cfi_offset %f0, 128
196+
#CHECK: .cfi_offset %f1, 136
197+
#CHECK: .cfi_offset %f2, 144
198+
#CHECK: .cfi_offset %f3, 152
199+
#CHECK: .cfi_offset %f4, 160
200+
#CHECK: .cfi_offset %f5, 168
201+
#CHECK: .cfi_offset %f6, 176
202+
#CHECK: .cfi_offset %f7, 184
203+
#CHECK: .cfi_offset %f8, 192
204+
#CHECK: .cfi_offset %f9, 200
205+
#CHECK: .cfi_offset %f10, 208
206+
#CHECK: .cfi_offset %f11, 216
207+
#CHECK: .cfi_offset %f12, 224
208+
#CHECK: .cfi_offset %f13, 232
209+
#CHECK: .cfi_offset %f14, 240
210+
#CHECK: .cfi_offset %f15, 248
211+
#CHECK: .cfi_offset %a0, 256
212+
#CHECK: .cfi_offset %a1, 260
213+
#CHECK: .cfi_offset %a2, 264
214+
#CHECK: .cfi_offset %a3, 268
215+
#CHECK: .cfi_offset %a4, 272
216+
#CHECK: .cfi_offset %a5, 276
217+
#CHECK: .cfi_offset %a6, 280
218+
#CHECK: .cfi_offset %a7, 284
219+
#CHECK: .cfi_offset %a8, 288
220+
#CHECK: .cfi_offset %r9, 292
221+
#CHECK: .cfi_offset %a10, 296
222+
#CHECK: .cfi_offset %a11, 300
223+
#CHECK: .cfi_offset %a12, 304
224+
#CHECK: .cfi_offset %a13, 308
225+
#CHECK: .cfi_offset %a14, 312
226+
#CHECK: .cfi_offset %a15, 316
227+
#CHECK: .cfi_offset %c0, 318
228+
#CHECK: .cfi_offset %c1, 326
229+
#CHECK: .cfi_offset %c2, 334
230+
#CHECK: .cfi_offset %c3, 342
231+
#CHECK: .cfi_offset %c4, 350
232+
#CHECK: .cfi_offset %c5, 358
233+
#CHECK: .cfi_offset %c6, 366
234+
#CHECK: .cfi_offset %c7, 374
235+
#CHECK: .cfi_offset %c8, 382
236+
#CHECK: .cfi_offset %c9, 390
237+
#CHECK: .cfi_offset %c10, 398
238+
#CHECK: .cfi_offset %c11, 406
239+
#CHECK: .cfi_offset %c12, 414
240+
#CHECK: .cfi_offset %c13, 422
241+
#CHECK: .cfi_offset %c14, 430
242+
#CHECK: .cfi_offset %c15, 438
179243
#CHECK: .cfi_offset %r0, 0
180244
#CHECK: .cfi_offset %r1, 8
181245
#CHECK: .cfi_offset %r2, 16
@@ -306,4 +370,68 @@
306370
.cfi_offset %c13,422
307371
.cfi_offset %c14,430
308372
.cfi_offset %c15,438
373+
.cfi_offset r0,0
374+
.cfi_offset r1,8
375+
.cfi_offset r2,16
376+
.cfi_offset r3,24
377+
.cfi_offset r4,32
378+
.cfi_offset r5,40
379+
.cfi_offset r6,48
380+
.cfi_offset r7,56
381+
.cfi_offset r8,64
382+
.cfi_offset r9,72
383+
.cfi_offset r10,80
384+
.cfi_offset r11,88
385+
.cfi_offset r12,96
386+
.cfi_offset r13,104
387+
.cfi_offset r14,112
388+
.cfi_offset r15,120
389+
.cfi_offset f0,128
390+
.cfi_offset f1,136
391+
.cfi_offset f2,144
392+
.cfi_offset f3,152
393+
.cfi_offset f4,160
394+
.cfi_offset f5,168
395+
.cfi_offset f6,176
396+
.cfi_offset f7,184
397+
.cfi_offset f8,192
398+
.cfi_offset f9,200
399+
.cfi_offset f10,208
400+
.cfi_offset f11,216
401+
.cfi_offset f12,224
402+
.cfi_offset f13,232
403+
.cfi_offset f14,240
404+
.cfi_offset f15,248
405+
.cfi_offset a0,256
406+
.cfi_offset a1,260
407+
.cfi_offset a2,264
408+
.cfi_offset a3,268
409+
.cfi_offset a4,272
410+
.cfi_offset a5,276
411+
.cfi_offset a6,280
412+
.cfi_offset a7,284
413+
.cfi_offset a8,288
414+
.cfi_offset r9,292
415+
.cfi_offset a10,296
416+
.cfi_offset a11,300
417+
.cfi_offset a12,304
418+
.cfi_offset a13,308
419+
.cfi_offset a14,312
420+
.cfi_offset a15,316
421+
.cfi_offset c0,318
422+
.cfi_offset c1,326
423+
.cfi_offset c2,334
424+
.cfi_offset c3,342
425+
.cfi_offset c4,350
426+
.cfi_offset c5,358
427+
.cfi_offset c6,366
428+
.cfi_offset c7,374
429+
.cfi_offset c8,382
430+
.cfi_offset c9,390
431+
.cfi_offset c10,398
432+
.cfi_offset c11,406
433+
.cfi_offset c12,414
434+
.cfi_offset c13,422
435+
.cfi_offset c14,430
436+
.cfi_offset c15,438
309437
.cfi_endproc

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