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lialanlialan
authored
Revert "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169546)
This reverts commit f67409c. cc @fiigii Including us, several separate groups are experiencing regressions with this change. This is the smallest reproducer pasted by @akuegel : #162930 (comment)
1 parent 97023fb commit ebf5d9e

17 files changed

+821
-2023
lines changed

‎llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp‎

Lines changed: 276 additions & 864 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -541,9 +541,10 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
541541
; GFX908-NEXT: s_lshr_b32 s2, s0, 16
542542
; GFX908-NEXT: v_cvt_f32_f16_e32 v19, s2
543543
; GFX908-NEXT: s_lshl_b64 s[6:7], s[4:5], 5
544-
; GFX908-NEXT: v_mov_b32_e32 v0, 0
545544
; GFX908-NEXT: s_lshl_b64 s[14:15], s[10:11], 5
545+
; GFX908-NEXT: v_mov_b32_e32 v0, 0
546546
; GFX908-NEXT: s_and_b64 s[0:1], exec, s[0:1]
547+
; GFX908-NEXT: s_or_b32 s14, s14, 28
547548
; GFX908-NEXT: s_lshl_b64 s[16:17], s[8:9], 5
548549
; GFX908-NEXT: v_mov_b32_e32 v1, 0
549550
; GFX908-NEXT: s_waitcnt vmcnt(0)
@@ -609,13 +610,13 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
609610
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
610611
; GFX908-NEXT: s_add_u32 s22, s20, s9
611612
; GFX908-NEXT: s_addc_u32 s23, s21, s13
612-
; GFX908-NEXT: global_load_dword v21, v17, s[22:23] offset:16 glc
613+
; GFX908-NEXT: global_load_dword v21, v17, s[22:23] offset:-12 glc
613614
; GFX908-NEXT: s_waitcnt vmcnt(0)
614-
; GFX908-NEXT: global_load_dword v20, v17, s[22:23] offset:20 glc
615+
; GFX908-NEXT: global_load_dword v20, v17, s[22:23] offset:-8 glc
615616
; GFX908-NEXT: s_waitcnt vmcnt(0)
616-
; GFX908-NEXT: global_load_dword v12, v17, s[22:23] offset:24 glc
617+
; GFX908-NEXT: global_load_dword v12, v17, s[22:23] offset:-4 glc
617618
; GFX908-NEXT: s_waitcnt vmcnt(0)
618-
; GFX908-NEXT: global_load_dword v12, v17, s[22:23] offset:28 glc
619+
; GFX908-NEXT: global_load_dword v12, v17, s[22:23] glc
619620
; GFX908-NEXT: s_waitcnt vmcnt(0)
620621
; GFX908-NEXT: ds_read_b64 v[12:13], v17
621622
; GFX908-NEXT: ds_read_b64 v[14:15], v0
@@ -709,6 +710,7 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
709710
; GFX90A-NEXT: s_lshl_b64 s[6:7], s[4:5], 5
710711
; GFX90A-NEXT: s_lshl_b64 s[14:15], s[10:11], 5
711712
; GFX90A-NEXT: s_and_b64 s[0:1], exec, s[0:1]
713+
; GFX90A-NEXT: s_or_b32 s14, s14, 28
712714
; GFX90A-NEXT: s_lshl_b64 s[16:17], s[8:9], 5
713715
; GFX90A-NEXT: s_waitcnt vmcnt(0)
714716
; GFX90A-NEXT: v_readfirstlane_b32 s2, v18
@@ -769,13 +771,13 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
769771
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
770772
; GFX90A-NEXT: s_add_u32 s22, s20, s9
771773
; GFX90A-NEXT: s_addc_u32 s23, s21, s13
772-
; GFX90A-NEXT: global_load_dword v21, v19, s[22:23] offset:16 glc
774+
; GFX90A-NEXT: global_load_dword v21, v19, s[22:23] offset:-12 glc
773775
; GFX90A-NEXT: s_waitcnt vmcnt(0)
774-
; GFX90A-NEXT: global_load_dword v20, v19, s[22:23] offset:20 glc
776+
; GFX90A-NEXT: global_load_dword v20, v19, s[22:23] offset:-8 glc
775777
; GFX90A-NEXT: s_waitcnt vmcnt(0)
776-
; GFX90A-NEXT: global_load_dword v14, v19, s[22:23] offset:24 glc
778+
; GFX90A-NEXT: global_load_dword v14, v19, s[22:23] offset:-4 glc
777779
; GFX90A-NEXT: s_waitcnt vmcnt(0)
778-
; GFX90A-NEXT: global_load_dword v14, v19, s[22:23] offset:28 glc
780+
; GFX90A-NEXT: global_load_dword v14, v19, s[22:23] glc
779781
; GFX90A-NEXT: s_waitcnt vmcnt(0)
780782
; GFX90A-NEXT: ds_read_b64 v[14:15], v19
781783
; GFX90A-NEXT: ds_read_b64 v[16:17], v0

‎llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -mtriple=amdgcn -amdgpu-scalar-ir-passes=false < %s | FileCheck %s
1+
; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
22

33
; Test for a bug where DAGCombiner::ReassociateOps() was creating adds
44
; with offset in the first operand and base pointers in the second.

‎llvm/test/CodeGen/AMDGPU/idot2.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2396,7 +2396,7 @@ define amdgpu_kernel void @udot2_MultipleUses_mul2(ptr addrspace(1) %src1,
23962396
; GFX9-NODL-NEXT: v_mul_u32_u24_e32 v4, v2, v1
23972397
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
23982398
; GFX9-NODL-NEXT: v_mad_u32_u24 v1, v2, v1, s0
2399-
; GFX9-NODL-NEXT: v_add3_u32 v1, v1, v4, v3
2399+
; GFX9-NODL-NEXT: v_add3_u32 v1, v4, v1, v3
24002400
; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
24012401
; GFX9-NODL-NEXT: s_endpgm
24022402
;
@@ -2417,7 +2417,7 @@ define amdgpu_kernel void @udot2_MultipleUses_mul2(ptr addrspace(1) %src1,
24172417
; GFX9-DL-NEXT: v_mul_u32_u24_e32 v4, v2, v1
24182418
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
24192419
; GFX9-DL-NEXT: v_mad_u32_u24 v1, v2, v1, s0
2420-
; GFX9-DL-NEXT: v_add3_u32 v1, v1, v4, v3
2420+
; GFX9-DL-NEXT: v_add3_u32 v1, v4, v1, v3
24212421
; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
24222422
; GFX9-DL-NEXT: s_endpgm
24232423
;
@@ -2442,7 +2442,7 @@ define amdgpu_kernel void @udot2_MultipleUses_mul2(ptr addrspace(1) %src1,
24422442
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
24432443
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v3, v0, s0
24442444
; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
2445-
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v2, v1
2445+
; GFX10-DL-NEXT: v_add3_u32 v0, v2, v0, v1
24462446
; GFX10-DL-NEXT: global_store_dword v3, v0, s[6:7]
24472447
; GFX10-DL-NEXT: s_endpgm
24482448
ptr addrspace(1) %src2,
@@ -2553,7 +2553,7 @@ define amdgpu_kernel void @idot2_MultipleUses_mul2(ptr addrspace(1) %src1,
25532553
; GFX9-NODL-NEXT: v_mul_i32_i24_e32 v4, v2, v1
25542554
; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
25552555
; GFX9-NODL-NEXT: v_mad_i32_i24 v1, v2, v1, s0
2556-
; GFX9-NODL-NEXT: v_add3_u32 v1, v1, v4, v3
2556+
; GFX9-NODL-NEXT: v_add3_u32 v1, v4, v1, v3
25572557
; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
25582558
; GFX9-NODL-NEXT: s_endpgm
25592559
;
@@ -2574,7 +2574,7 @@ define amdgpu_kernel void @idot2_MultipleUses_mul2(ptr addrspace(1) %src1,
25742574
; GFX9-DL-NEXT: v_mul_i32_i24_e32 v4, v2, v1
25752575
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
25762576
; GFX9-DL-NEXT: v_mad_i32_i24 v1, v2, v1, s0
2577-
; GFX9-DL-NEXT: v_add3_u32 v1, v1, v4, v3
2577+
; GFX9-DL-NEXT: v_add3_u32 v1, v4, v1, v3
25782578
; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
25792579
; GFX9-DL-NEXT: s_endpgm
25802580
;
@@ -2599,7 +2599,7 @@ define amdgpu_kernel void @idot2_MultipleUses_mul2(ptr addrspace(1) %src1,
25992599
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
26002600
; GFX10-DL-NEXT: v_mad_i32_i24 v0, v3, v0, s0
26012601
; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
2602-
; GFX10-DL-NEXT: v_add3_u32 v0, v0, v2, v1
2602+
; GFX10-DL-NEXT: v_add3_u32 v0, v2, v0, v1
26032603
; GFX10-DL-NEXT: global_store_dword v3, v0, s[6:7]
26042604
; GFX10-DL-NEXT: s_endpgm
26052605
ptr addrspace(1) %src2,

‎llvm/test/CodeGen/AMDGPU/idot4s.ll‎

Lines changed: 79 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -3268,19 +3268,19 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
32683268
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
32693269
; GFX7-NEXT: s_mov_b32 s2, -1
32703270
; GFX7-NEXT: s_waitcnt vmcnt(1)
3271-
; GFX7-NEXT: v_bfe_i32 v3, v2, 8, 8
32723271
; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
3272+
; GFX7-NEXT: v_bfe_i32 v3, v2, 8, 8
3273+
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
32733274
; GFX7-NEXT: s_waitcnt vmcnt(0)
3275+
; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
3276+
; GFX7-NEXT: v_bfe_i32 v4, v2, 16, 8
32743277
; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
32753278
; GFX7-NEXT: v_and_b32_e32 v3, 0xffff, v3
3276-
; GFX7-NEXT: v_bfe_i32 v4, v2, 16, 8
3277-
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
3278-
; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
3279-
; GFX7-NEXT: v_mul_u32_u24_e32 v3, v6, v3
3279+
; GFX7-NEXT: v_mul_u32_u24_e32 v1, v1, v5
32803280
; GFX7-NEXT: v_ashrrev_i32_e32 v2, 24, v2
32813281
; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8
32823282
; GFX7-NEXT: v_and_b32_e32 v4, 0xffff, v4
3283-
; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, v3
3283+
; GFX7-NEXT: v_mad_u32_u24 v1, v6, v3, v1
32843284
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0
32853285
; GFX7-NEXT: v_mad_u32_u24 v1, v7, v4, v1
32863286
; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -3307,18 +3307,18 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
33073307
; GFX8-NEXT: v_mov_b32_e32 v0, s4
33083308
; GFX8-NEXT: v_mov_b32_e32 v1, s5
33093309
; GFX8-NEXT: s_waitcnt vmcnt(1)
3310-
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 8, v3
3310+
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 8, v3
33113311
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3
3312-
; GFX8-NEXT: v_bfe_i32 v6, v3, 0, 8
3313-
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
3312+
; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 8
33143313
; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 8
3315-
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 8
33163314
; GFX8-NEXT: s_waitcnt vmcnt(0)
3317-
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v2
3318-
; GFX8-NEXT: v_and_b32_e32 v7, 0xff, v2
3319-
; GFX8-NEXT: v_mul_lo_u16_sdwa v8, v9, sext(v8) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
3315+
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 8, v2
3316+
; GFX8-NEXT: v_mul_lo_u16_sdwa v6, sext(v3), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
3317+
; GFX8-NEXT: v_and_b32_e32 v8, 0xff, v8
33203318
; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
3321-
; GFX8-NEXT: v_mad_u16 v6, v6, v7, v8
3319+
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
3320+
; GFX8-NEXT: v_mad_u16 v6, v8, v7, v6
3321+
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 8
33223322
; GFX8-NEXT: v_mad_u16 v4, v4, v5, v6
33233323
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v2
33243324
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v4
@@ -3337,19 +3337,19 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
33373337
; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff
33383338
; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
33393339
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
3340-
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
3340+
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
33413341
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
3342-
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
3342+
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v6, 8, v2
33433343
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
3344-
; GFX9-NODL-NEXT: v_bfe_i32 v4, v1, 0, 8
3345-
; GFX9-NODL-NEXT: v_and_b32_e32 v5, 0xff, v2
3346-
; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v6, v7, sext(v6) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
3347-
; GFX9-NODL-NEXT: v_and_b32_sdwa v8, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
3344+
; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v4, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
3345+
; GFX9-NODL-NEXT: v_bfe_i32 v5, v5, 0, 8
3346+
; GFX9-NODL-NEXT: v_and_b32_e32 v6, 0xff, v6
3347+
; GFX9-NODL-NEXT: v_and_b32_sdwa v7, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
33483348
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
33493349
; GFX9-NODL-NEXT: v_bfe_i32 v3, v3, 0, 8
3350-
; GFX9-NODL-NEXT: v_mad_legacy_u16 v4, v4, v5, v6
3350+
; GFX9-NODL-NEXT: v_mad_legacy_u16 v4, v6, v5, v4
33513351
; GFX9-NODL-NEXT: v_bfe_i32 v1, v1, 0, 8
3352-
; GFX9-NODL-NEXT: v_mad_legacy_u16 v3, v8, v3, v4
3352+
; GFX9-NODL-NEXT: v_mad_legacy_u16 v3, v7, v3, v4
33533353
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
33543354
; GFX9-NODL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
33553355
; GFX9-NODL-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -3367,19 +3367,19 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
33673367
; GFX9-DL-NEXT: s_movk_i32 s0, 0xff
33683368
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
33693369
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
3370-
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
3370+
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
33713371
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
3372-
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
3372+
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v2
33733373
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
3374-
; GFX9-DL-NEXT: v_bfe_i32 v4, v1, 0, 8
3375-
; GFX9-DL-NEXT: v_and_b32_e32 v5, 0xff, v2
3376-
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v7, sext(v6) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
3377-
; GFX9-DL-NEXT: v_and_b32_sdwa v8, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
3374+
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
3375+
; GFX9-DL-NEXT: v_bfe_i32 v5, v5, 0, 8
3376+
; GFX9-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
3377+
; GFX9-DL-NEXT: v_and_b32_sdwa v7, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
33783378
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
33793379
; GFX9-DL-NEXT: v_bfe_i32 v3, v3, 0, 8
3380-
; GFX9-DL-NEXT: v_mad_legacy_u16 v4, v4, v5, v6
3380+
; GFX9-DL-NEXT: v_mad_legacy_u16 v4, v6, v5, v4
33813381
; GFX9-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
3382-
; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v8, v3, v4
3382+
; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v7, v3, v4
33833383
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
33843384
; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
33853385
; GFX9-DL-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -3392,28 +3392,28 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
33923392
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
33933393
; GFX10-DL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
33943394
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
3395-
; GFX10-DL-NEXT: v_mov_b32_e32 v4, 0xff
3395+
; GFX10-DL-NEXT: v_mov_b32_e32 v6, 0xff
33963396
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
33973397
; GFX10-DL-NEXT: s_clause 0x1
33983398
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
33993399
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
34003400
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
3401-
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v1
3401+
; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 8
34023402
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
3403-
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v2
3404-
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
3405-
; GFX10-DL-NEXT: v_bfe_i32 v6, v1, 0, 8
3406-
; GFX10-DL-NEXT: v_and_b32_e32 v7, 0xff, v2
3407-
; GFX10-DL-NEXT: v_bfe_i32 v0, v0, 0, 8
3408-
; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xff, v3
3403+
; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xff, v2
3404+
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v1
3405+
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v2
3406+
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v1
34093407
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
3410-
; GFX10-DL-NEXT: v_mul_lo_u16 v0, v3, v0
3411-
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
3412-
; GFX10-DL-NEXT: v_bfe_i32 v4, v5, 0, 8
3408+
; GFX10-DL-NEXT: v_mul_lo_u16 v0, v0, v3
3409+
; GFX10-DL-NEXT: v_bfe_i32 v3, v4, 0, 8
3410+
; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v5
3411+
; GFX10-DL-NEXT: v_and_b32_sdwa v5, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
3412+
; GFX10-DL-NEXT: v_bfe_i32 v6, v7, 0, 8
34133413
; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
34143414
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
3415-
; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
3416-
; GFX10-DL-NEXT: v_mad_u16 v0, v3, v4, v0
3415+
; GFX10-DL-NEXT: v_mad_u16 v0, v4, v3, v0
3416+
; GFX10-DL-NEXT: v_mad_u16 v0, v5, v6, v0
34173417
; GFX10-DL-NEXT: v_mad_u16 v0, v1, v2, v0
34183418
; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
34193419
; GFX10-DL-NEXT: v_bfe_i32 v0, v0, 0, 16
@@ -3429,34 +3429,32 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
34293429
; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
34303430
; GFX11-DL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
34313431
; GFX11-DL-TRUE16-NEXT: s_clause 0x1
3432-
; GFX11-DL-TRUE16-NEXT: global_load_b32 v3, v0, s[0:1]
3433-
; GFX11-DL-TRUE16-NEXT: global_load_b32 v4, v0, s[2:3]
3432+
; GFX11-DL-TRUE16-NEXT: global_load_b32 v2, v0, s[0:1]
3433+
; GFX11-DL-TRUE16-NEXT: global_load_b32 v3, v0, s[2:3]
34343434
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1)
3435-
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 8, v3
3435+
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v2
3436+
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 8
34363437
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
3437-
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4
3438-
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v3, 0, 8
3439-
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.h
3440-
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v0, 0, 8
3441-
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
3442-
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l
3443-
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v4.l
3444-
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
3445-
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
3438+
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l
3439+
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v3
3440+
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
3441+
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8
3442+
; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.h
3443+
; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l
3444+
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v5.l
34463445
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8
3447-
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v3
3448-
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
3449-
; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
3450-
; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v4.h
3451-
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
3452-
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 24, v4
3453-
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
3454-
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v0.h, v0.l
3455-
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
3456-
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v3.l, v0.l
3446+
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l
3447+
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 24, v2
3448+
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
3449+
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
3450+
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
3451+
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v1.l, v0.l
3452+
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
3453+
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8
3454+
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.h, v2.l, v0.l
34573455
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
3458-
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
3459-
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v4.l, v0.l
3456+
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l
3457+
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v3.l, v0.l
34603458
; GFX11-DL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
34613459
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
34623460
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
@@ -3475,25 +3473,24 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
34753473
; GFX11-DL-FAKE16-NEXT: global_load_b32 v1, v0, s[0:1]
34763474
; GFX11-DL-FAKE16-NEXT: global_load_b32 v0, v0, s[2:3]
34773475
; GFX11-DL-FAKE16-NEXT: s_waitcnt vmcnt(1)
3478-
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v1
3476+
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v2, v1, 0, 8
34793477
; GFX11-DL-FAKE16-NEXT: s_waitcnt vmcnt(0)
3480-
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v0
3481-
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
3482-
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
3483-
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v6, v1, 0, 8
3484-
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
3485-
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
3486-
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v0
3487-
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 24, v1
3488-
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 24, v0
3489-
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
3490-
; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v2, v3, v2
3478+
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v0
3479+
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 8, v1
3480+
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v0
3481+
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
3482+
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
3483+
; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v2, v2, v3
34913484
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v3, v4, 0, 8
34923485
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
3493-
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
3494-
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v2, v6, v7, v2
3495-
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
3486+
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 24, v1
3487+
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v5, v6, 0, 8
3488+
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
3489+
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 24, v0
34963490
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v2, v4, v3, v2
3491+
; GFX11-DL-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
3492+
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
3493+
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v2, v6, v5, v2
34973494
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v0, v1, v0, v2
34983495
; GFX11-DL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
34993496
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)

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