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%a.lane.0 = fmul double %v1.lane.0 , %v2.lane.2
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%a.lane.1 = fmul double %v1.lane.1 , %v2.lane.3
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- %a.ins.0 = insertelement <2 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <2 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <2 x double > %a.ins.0 , double %a.lane.1 , i32 1
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call void @use (double %v1.lane.0 )
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%a.lane.0 = fmul double %v1.lane.0 , %v2.lane.2
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%a.lane.1 = fmul double %v3.lane.1 , %v2.lane.2
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- %a.ins.0 = insertelement <2 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <2 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <2 x double > %a.ins.0 , double %a.lane.1 , i32 1
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call void @use (double %v1.lane.0 )
@@ -95,7 +95,8 @@ define void @noop_extract_second_2_lanes(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_1]], <4 x double> poison, <2 x i32> <i32 2, i32 3>
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
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- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
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; CHECK-NEXT: call void @use(double [[V1_LANE_3]])
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; CHECK-NEXT: store <4 x double> [[TMP3]], ptr [[PTR_1]], align 8
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%a.lane.0 = fmul double %v1.lane.2 , %v2.lane.2
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%a.lane.1 = fmul double %v1.lane.3 , %v2.lane.2
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- %a.ins.0 = insertelement <4 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <4 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <4 x double > %a.ins.0 , double %a.lane.1 , i32 1
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call void @use (double %v1.lane.2 )
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%a.lane.0 = fmul double %v1.lane.1 , %v2.lane.2
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%a.lane.1 = fmul double %v1.lane.0 , %v2.lane.2
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- %a.ins.0 = insertelement <2 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <2 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <2 x double > %a.ins.0 , double %a.lane.1 , i32 1
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call void @use (double %v1.lane.0 )
@@ -170,7 +171,8 @@ define void @extract_lanes_1_and_2(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[V_1]], <4 x double> poison, <2 x i32> <i32 1, i32 2>
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], [[TMP1]]
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- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
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; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
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; CHECK-NEXT: store <4 x double> [[TMP3]], ptr [[PTR_1]], align 8
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%a.lane.0 = fmul double %v1.lane.1 , %v2.lane.2
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%a.lane.1 = fmul double %v1.lane.2 , %v2.lane.2
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- %a.ins.0 = insertelement <4 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <4 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <4 x double > %a.ins.0 , double %a.lane.1 , i32 1
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call void @use (double %v1.lane.1 )
@@ -213,7 +215,8 @@ define void @noop_extracts_existing_vector_4_lanes(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <4 x i32> <i32 2, i32 0, i32 2, i32 2>
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP0]], [[TMP1]]
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- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> undef, <9 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7, i32 7>
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+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <9 x i32> <i32 2, i32 3, i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP4]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 4, i32 5, i32 6, i32 7, i32 8>
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; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
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; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
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; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
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%a.lane.1 = fmul double %v1.lane.3 , %v2.lane.2
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%a.lane.2 = fmul double %v1.lane.0 , %v2.lane.2
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%a.lane.3 = fmul double %v1.lane.1 , %v2.lane.0
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- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
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%a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
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%a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
@@ -261,7 +264,8 @@ define void @extracts_jumbled_4_lanes(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V_2]], <4 x double> poison, <4 x i32> <i32 2, i32 2, i32 1, i32 0>
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP0]], [[TMP1]]
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- ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> undef, <9 x i32> <i32 0, i32 2, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7>
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+ ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <9 x i32> <i32 0, i32 2, i32 1, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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+ ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP4]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 4, i32 5, i32 6, i32 7, i32 8>
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; CHECK-NEXT: call void @use(double [[V1_LANE_0]])
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; CHECK-NEXT: call void @use(double [[V1_LANE_1]])
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; CHECK-NEXT: call void @use(double [[V1_LANE_2]])
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%a.lane.1 = fmul double %v1.lane.2 , %v2.lane.1
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%a.lane.2 = fmul double %v1.lane.1 , %v2.lane.2
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%a.lane.3 = fmul double %v1.lane.3 , %v2.lane.0
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- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
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%a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
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%a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
@@ -313,12 +317,14 @@ define void @noop_extracts_9_lanes(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_0]]
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
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- ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[TMP3]], double [[A_LANE_8]], i32 8
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+ ; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
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+ ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 6, i32 7, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
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; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> [[TMP4]], [[TMP5]]
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; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_5]], [[V2_LANE_0]]
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
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- ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[TMP7]], double [[B_LANE_8]], i32 8
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+ ; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP7]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
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+ ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
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; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
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; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
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; CHECK-NEXT: ret void
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%a.lane.7 = fmul double %v1.lane.1 , %v2.lane.1
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%a.lane.8 = fmul double %v1.lane.2 , %v2.lane.0
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- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
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%a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
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%a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
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%b.lane.7 = fmul double %v1.lane.4 , %v2.lane.1
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%b.lane.8 = fmul double %v1.lane.5 , %v2.lane.0
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- %b.ins.0 = insertelement <9 x double > undef , double %b.lane.0 , i32 0
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+ %b.ins.0 = insertelement <9 x double > zeroinitializer , double %b.lane.0 , i32 0
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%b.ins.1 = insertelement <9 x double > %b.ins.0 , double %b.lane.1 , i32 1
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%b.ins.2 = insertelement <9 x double > %b.ins.1 , double %b.lane.2 , i32 2
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%b.ins.3 = insertelement <9 x double > %b.ins.2 , double %b.lane.3 , i32 3
@@ -401,12 +407,14 @@ define void @first_mul_chain_jumbled(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[V2_LANE_1:%.*]] = extractelement <4 x double> [[V_2]], i32 1
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; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_1]]
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
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- ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[TMP3]], double [[A_LANE_8]], i32 8
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+ ; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
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+ ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 6, i32 7, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
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; CHECK-NEXT: [[TMP5:%.*]] = fmul <8 x double> [[TMP4]], [[TMP1]]
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; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_5]], [[V2_LANE_0]]
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> [[TMP5]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
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- ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[TMP6]], double [[B_LANE_8]], i32 8
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+ ; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP6]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
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+ ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
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; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
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; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
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; CHECK-NEXT: ret void
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%a.lane.7 = fmul double %v1.lane.0 , %v2.lane.2
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%a.lane.8 = fmul double %v1.lane.2 , %v2.lane.1
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- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
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%a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
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%a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
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%b.lane.7 = fmul double %v1.lane.4 , %v2.lane.2
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%b.lane.8 = fmul double %v1.lane.5 , %v2.lane.0
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- %b.ins.0 = insertelement <9 x double > undef , double %b.lane.0 , i32 0
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+ %b.ins.0 = insertelement <9 x double > zeroinitializer , double %b.lane.0 , i32 0
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%b.ins.1 = insertelement <9 x double > %b.ins.0 , double %b.lane.1 , i32 1
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%b.ins.2 = insertelement <9 x double > %b.ins.1 , double %b.lane.2 , i32 2
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%b.ins.3 = insertelement <9 x double > %b.ins.2 , double %b.lane.3 , i32 3
@@ -490,12 +498,14 @@ define void @first_and_second_mul_chain_jumbled(ptr %ptr.1, ptr %ptr.2) {
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; CHECK-NEXT: [[TMP2:%.*]] = fmul <8 x double> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[A_LANE_8:%.*]] = fmul double [[V1_LANE_2]], [[V2_LANE_0]]
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
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- ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[TMP3]], double [[A_LANE_8]], i32 8
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+ ; CHECK-NEXT: [[A_INS_72:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP3]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
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+ ; CHECK-NEXT: [[A_INS_8:%.*]] = insertelement <9 x double> [[A_INS_72]], double [[A_LANE_8]], i32 8
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <9 x double> [[V_1]], <9 x double> poison, <8 x i32> <i32 7, i32 6, i32 8, i32 1, i32 0, i32 3, i32 2, i32 5>
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; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> [[TMP4]], [[TMP5]]
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; CHECK-NEXT: [[B_LANE_8:%.*]] = fmul double [[V1_LANE_4]], [[V2_LANE_2]]
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
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- ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[TMP7]], double [[B_LANE_8]], i32 8
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+ ; CHECK-NEXT: [[B_INS_71:%.*]] = shufflevector <9 x double> zeroinitializer, <9 x double> [[TMP7]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
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+ ; CHECK-NEXT: [[B_INS_8:%.*]] = insertelement <9 x double> [[B_INS_71]], double [[B_LANE_8]], i32 8
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; CHECK-NEXT: [[RES:%.*]] = fsub <9 x double> [[A_INS_8]], [[B_INS_8]]
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; CHECK-NEXT: store <9 x double> [[RES]], ptr [[PTR_1]], align 8
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; CHECK-NEXT: ret void
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%a.lane.7 = fmul double %v1.lane.0 , %v2.lane.1
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%a.lane.8 = fmul double %v1.lane.2 , %v2.lane.0
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- %a.ins.0 = insertelement <9 x double > undef , double %a.lane.0 , i32 0
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+ %a.ins.0 = insertelement <9 x double > zeroinitializer , double %a.lane.0 , i32 0
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%a.ins.1 = insertelement <9 x double > %a.ins.0 , double %a.lane.1 , i32 1
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%a.ins.2 = insertelement <9 x double > %a.ins.1 , double %a.lane.2 , i32 2
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%a.ins.3 = insertelement <9 x double > %a.ins.2 , double %a.lane.3 , i32 3
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%b.lane.7 = fmul double %v1.lane.5 , %v2.lane.0
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%b.lane.8 = fmul double %v1.lane.4 , %v2.lane.2
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- %b.ins.0 = insertelement <9 x double > undef , double %b.lane.0 , i32 0
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+ %b.ins.0 = insertelement <9 x double > zeroinitializer , double %b.lane.0 , i32 0
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%b.ins.1 = insertelement <9 x double > %b.ins.0 , double %b.lane.1 , i32 1
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%b.ins.2 = insertelement <9 x double > %b.ins.1 , double %b.lane.2 , i32 2
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%b.ins.3 = insertelement <9 x double > %b.ins.2 , double %b.lane.3 , i32 3
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