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Declare builtins to take MachineType
1 parent 2ea18ad commit ec017e3

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3 files changed

+25
-49
lines changed

3 files changed

+25
-49
lines changed

‎clang/include/clang/Basic/BuiltinsRISCVXCV.def‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -21,21 +21,21 @@ TARGET_BUILTIN(alu_min, "ZiZiZi", "nc", "xcvalu")
2121
TARGET_BUILTIN(alu_minu, "UZiUZiUZi", "nc", "xcvalu")
2222
TARGET_BUILTIN(alu_max, "ZiZiZi", "nc", "xcvalu")
2323
TARGET_BUILTIN(alu_maxu, "UZiUZiUZi", "nc", "xcvalu")
24-
TARGET_BUILTIN(alu_exths, "Zis", "nc", "xcvalu")
25-
TARGET_BUILTIN(alu_exthz, "UZiUs", "nc", "xcvalu")
26-
TARGET_BUILTIN(alu_extbs, "Zic", "nc", "xcvalu")
27-
TARGET_BUILTIN(alu_extbz, "UZiUc", "nc", "xcvalu")
24+
TARGET_BUILTIN(alu_exths, "Zii", "nc", "xcvalu")
25+
TARGET_BUILTIN(alu_exthz, "UZiUi", "nc", "xcvalu")
26+
TARGET_BUILTIN(alu_extbs, "Zii", "nc", "xcvalu")
27+
TARGET_BUILTIN(alu_extbz, "UZiUi", "nc", "xcvalu")
2828

2929
TARGET_BUILTIN(alu_clip, "ZiZiUZi", "nc", "xcvalu")
3030
TARGET_BUILTIN(alu_clipu, "UZiUZiUZi", "nc", "xcvalu")
31-
TARGET_BUILTIN(alu_addN, "ZiZiUZiUc", "nc", "xcvalu")
32-
TARGET_BUILTIN(alu_adduN, "UZiUZiUZiUc", "nc", "xcvalu")
33-
TARGET_BUILTIN(alu_addRN, "ZiZiZiUc", "nc", "xcvalu")
34-
TARGET_BUILTIN(alu_adduRN, "UZiUZiUZiUc", "nc", "xcvalu")
35-
TARGET_BUILTIN(alu_subN, "ZiZiUZiUc", "nc", "xcvalu")
36-
TARGET_BUILTIN(alu_subuN, "UZiUZiUZiUc", "nc", "xcvalu")
37-
TARGET_BUILTIN(alu_subRN, "ZiZiZiUc", "nc", "xcvalu")
38-
TARGET_BUILTIN(alu_subuRN, "UZiUZiUZiUc", "nc", "xcvalu")
31+
TARGET_BUILTIN(alu_addN, "ZiZiUZiUi", "nc", "xcvalu")
32+
TARGET_BUILTIN(alu_adduN, "UZiUZiUZiUi", "nc", "xcvalu")
33+
TARGET_BUILTIN(alu_addRN, "ZiZiZiUi", "nc", "xcvalu")
34+
TARGET_BUILTIN(alu_adduRN, "UZiUZiUZiUi", "nc", "xcvalu")
35+
TARGET_BUILTIN(alu_subN, "ZiZiUZiUi", "nc", "xcvalu")
36+
TARGET_BUILTIN(alu_subuN, "UZiUZiUZiUi", "nc", "xcvalu")
37+
TARGET_BUILTIN(alu_subRN, "ZiZiZiUi", "nc", "xcvalu")
38+
TARGET_BUILTIN(alu_subuRN, "UZiUZiUZiUi", "nc", "xcvalu")
3939

4040
#undef BUILTIN
4141
#undef TARGET_BUILTIN

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 1 addition & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -22114,30 +22114,6 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
2211422114
return nullptr;
2211522115
}
2211622116

22117-
static Value *EmitXCVIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
22118-
unsigned IntrinsicID,
22119-
MutableArrayRef<Value *> Ops,
22120-
const CallExpr *E) {
22121-
llvm::Type *MachineType =
22122-
llvm::IntegerType::getInt32Ty(CGF.CGM.getLLVMContext());
22123-
for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
22124-
if (Ops[i]->getType() != MachineType) {
22125-
QualType type = E->getArg(i)->getType();
22126-
assert((type->isSignedIntegerType() || type->isUnsignedIntegerType() ||
22127-
type->isPointerType()) &&
22128-
"Argument of Core-V builtin must have signed or unsigned integer "
22129-
"or Pointer type");
22130-
if (type->isSignedIntegerType()) {
22131-
Ops[i] = CGF.Builder.CreateSExt(Ops[i], MachineType);
22132-
} else if ((type->isUnsignedIntegerType())) {
22133-
Ops[i] = CGF.Builder.CreateZExt(Ops[i], MachineType);
22134-
}
22135-
}
22136-
}
22137-
llvm::Function *F = CGF.CGM.getIntrinsic(IntrinsicID);
22138-
return CGF.Builder.CreateCall(F, Ops);
22139-
}
22140-
2214122117
Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2214222118
const CallExpr *E,
2214322119
ReturnValueSlot ReturnValue) {
@@ -22368,7 +22344,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2236822344
#define BUILTIN(NAME, TYPE, ATTRS) \
2236922345
case RISCVXCV::BI__builtin_riscv_cv_##NAME: \
2237022346
ID = Intrinsic::riscv_cv_##NAME; \
22371-
return EmitXCVIntrinsic(*this, BuiltinID, ID, Ops, E);
22347+
return Builder.CreateCall(CGM.getIntrinsic(ID), Ops);
2237222348
#include "clang/Basic/BuiltinsRISCVXCV.def"
2237322349

2237422350
// Vector builtins are handled from here.

‎clang/test/CodeGen/RISCV/riscv-xcvalu.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -111,9 +111,9 @@ int test_alu_maxu(uint32_t a, uint32_t b) {
111111
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
112112
// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR]], align 2
113113
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
114-
// CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TMP0]] to i32
115-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.exths(i32 [[TMP1]])
116-
// CHECK-NEXT: ret i32 [[TMP2]]
114+
// CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
115+
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.exths(i32 [[CONV]])
116+
// CHECK-NEXT: ret i32 [[TMP1]]
117117
//
118118
int test_alu_exths(int16_t a) {
119119
return __builtin_riscv_cv_alu_exths(a);
@@ -124,9 +124,9 @@ int test_alu_exths(int16_t a) {
124124
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
125125
// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR]], align 2
126126
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
127-
// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
128-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.exthz(i32 [[TMP1]])
129-
// CHECK-NEXT: ret i32 [[TMP2]]
127+
// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32
128+
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.exthz(i32 [[CONV]])
129+
// CHECK-NEXT: ret i32 [[TMP1]]
130130
//
131131
int test_alu_exthz(uint16_t a) {
132132
return __builtin_riscv_cv_alu_exthz(a);
@@ -137,9 +137,9 @@ int test_alu_exthz(uint16_t a) {
137137
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i8, align 1
138138
// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1
139139
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
140-
// CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[TMP0]] to i32
141-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.extbs(i32 [[TMP1]])
142-
// CHECK-NEXT: ret i32 [[TMP2]]
140+
// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32
141+
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.extbs(i32 [[CONV]])
142+
// CHECK-NEXT: ret i32 [[TMP1]]
143143
//
144144
int test_alu_extbs(int8_t a) {
145145
return __builtin_riscv_cv_alu_extbs(a);
@@ -150,9 +150,9 @@ int test_alu_extbs(int8_t a) {
150150
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i8, align 1
151151
// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1
152152
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
153-
// CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
154-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.extbz(i32 [[TMP1]])
155-
// CHECK-NEXT: ret i32 [[TMP2]]
153+
// CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
154+
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.extbz(i32 [[CONV]])
155+
// CHECK-NEXT: ret i32 [[TMP1]]
156156
//
157157
int test_alu_extbz(uint8_t a) {
158158
return __builtin_riscv_cv_alu_extbz(a);

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