[bazel] Reorder targets

Author: chapuni

utils/bazel/llvm-project-overlay/llvm/BUILD.bazel

@@ -2222,6 +2222,29 @@ llvm_target_lib_list = [lib for lib in [
             ("-gen-exegesis", "lib/Target/PowerPC/PPCGenExegesis.inc"),
         ],
     },
+    {
+        "name": "RISCV",
+        "short_name": "RISCV",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "lib/Target/RISCV/RISCVGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "lib/Target/RISCV/RISCVGenAsmWriter.inc"),
+            ("-gen-compress-inst-emitter", "lib/Target/RISCV/RISCVGenCompressInstEmitter.inc"),
+            ("-gen-dag-isel", "lib/Target/RISCV/RISCVGenDAGISel.inc"),
+            ("-gen-disassembler", "lib/Target/RISCV/RISCVGenDisassemblerTables.inc"),
+            ("-gen-instr-info", "lib/Target/RISCV/RISCVGenInstrInfo.inc"),
+            ("-gen-macro-fusion-pred", "lib/Target/RISCV/RISCVGenMacroFusion.inc"),
+            ("-gen-emitter", "lib/Target/RISCV/RISCVGenMCCodeEmitter.inc"),
+            ("-gen-pseudo-lowering", "lib/Target/RISCV/RISCVGenMCPseudoLowering.inc"),
+            ("-gen-register-bank", "lib/Target/RISCV/RISCVGenRegisterBank.inc"),
+            ("-gen-register-info", "lib/Target/RISCV/RISCVGenRegisterInfo.inc"),
+            ("-gen-subtarget", "lib/Target/RISCV/RISCVGenSubtargetInfo.inc"),
+            ("-gen-searchable-tables", "lib/Target/RISCV/RISCVGenSearchableTables.inc"),
+            ("-gen-exegesis", "lib/Target/RISCV/RISCVGenExegesis.inc"),
+        ],
+        "tbl_deps": [
+            ":riscv_isel_target_gen",
+        ],
+    },
     {
         "name": "Sparc",
         "short_name": "Sparc",
@@ -2269,29 +2292,6 @@ llvm_target_lib_list = [lib for lib in [
             ("-gen-subtarget", "lib/Target/SystemZ/SystemZGenSubtargetInfo.inc"),
         ],
     },
-    {
-        "name": "RISCV",
-        "short_name": "RISCV",
-        "tbl_outs": [
-            ("-gen-asm-matcher", "lib/Target/RISCV/RISCVGenAsmMatcher.inc"),
-            ("-gen-asm-writer", "lib/Target/RISCV/RISCVGenAsmWriter.inc"),
-            ("-gen-compress-inst-emitter", "lib/Target/RISCV/RISCVGenCompressInstEmitter.inc"),
-            ("-gen-dag-isel", "lib/Target/RISCV/RISCVGenDAGISel.inc"),
-            ("-gen-disassembler", "lib/Target/RISCV/RISCVGenDisassemblerTables.inc"),
-            ("-gen-instr-info", "lib/Target/RISCV/RISCVGenInstrInfo.inc"),
-            ("-gen-macro-fusion-pred", "lib/Target/RISCV/RISCVGenMacroFusion.inc"),
-            ("-gen-emitter", "lib/Target/RISCV/RISCVGenMCCodeEmitter.inc"),
-            ("-gen-pseudo-lowering", "lib/Target/RISCV/RISCVGenMCPseudoLowering.inc"),
-            ("-gen-register-bank", "lib/Target/RISCV/RISCVGenRegisterBank.inc"),
-            ("-gen-register-info", "lib/Target/RISCV/RISCVGenRegisterInfo.inc"),
-            ("-gen-subtarget", "lib/Target/RISCV/RISCVGenSubtargetInfo.inc"),
-            ("-gen-searchable-tables", "lib/Target/RISCV/RISCVGenSearchableTables.inc"),
-            ("-gen-exegesis", "lib/Target/RISCV/RISCVGenExegesis.inc"),
-        ],
-        "tbl_deps": [
-            ":riscv_isel_target_gen",
-        ],
-    },
     {
         "name": "VE",
         "short_name": "VE",