Allow any type

Author: rovka

llvm/include/llvm/IR/IntrinsicsAMDGPU.td

@@ -3455,6 +3455,6 @@ def int_amdgcn_addrspacecast_nonnull : DefaultAttrsIntrinsic<
 /// when used as an input to a phi node, it will make it possible for the
 /// backend to allocate the dead lanes for operations within the corresponding
 /// incoming block.
-def int_amdgcn_dead: DefaultAttrsIntrinsic<[llvm_i32_ty], [],
+def int_amdgcn_dead: DefaultAttrsIntrinsic<[llvm_any_ty], [],
     [IntrNoMem, IntrWillReturn, IntrNoCallback]>;
 }

llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll

@@ -520,9 +520,9 @@ define amdgpu_kernel void @v_permlane32_swap(ptr addrspace(1) %out, i32 %src0, i
   ret void
 }
 
-; CHECK: DIVERGENT:   %v = call i32 @llvm.amdgcn.dead()
+; CHECK: DIVERGENT:   %v = call i32 @llvm.amdgcn.dead.i32()
 define amdgpu_cs_chain void @dead(ptr addrspace(1) %out) {
-  %v = call i32 @llvm.amdgcn.dead()
+  %v = call i32 @llvm.amdgcn.dead.i32()
   store i32 %v, ptr addrspace(1) %out
   ret void
 }
@@ -563,7 +563,7 @@ declare <4 x i16> @llvm.amdgcn.global.load.tr.b128.v4i16(ptr addrspace(1))
 declare <4 x half> @llvm.amdgcn.global.load.tr.b128.v4f16(ptr addrspace(1))
 declare <4 x bfloat> @llvm.amdgcn.global.load.tr.b128.v4bf16(ptr addrspace(1))
 
-declare i32 @llvm.amdgcn.dead()
+declare i32 @llvm.amdgcn.dead.i32()
 
 attributes #0 = { nounwind convergent }
 attributes #1 = { nounwind readnone convergent }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll

@@ -50,7 +50,7 @@ define i32 @dead(i1 %cond, i32 %x, ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr
 ; ASM-GISEL-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; ASM-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
-  %dead = call i32 @llvm.amdgcn.dead()
+  %dead = call i32 @llvm.amdgcn.dead.i32()
   br i1 %cond, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry