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davemgreendavemgreen
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[ARM] Add neon vector support for rint
As per #142559, this marks frint as legal for Neon and upgrades the existing arm.neon.vrintx intrinsics.
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8 files changed

+17
-61
lines changed

8 files changed

+17
-61
lines changed

‎clang/lib/CodeGen/TargetBuiltins/ARM.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -850,8 +850,8 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
850850
NEONMAP1(vrndp_v, ceil, Add1ArgType),
851851
NEONMAP1(vrndpq_v, ceil, Add1ArgType),
852852
NEONMAP1(vrndq_v, trunc, Add1ArgType),
853-
NEONMAP1(vrndx_v, arm_neon_vrintx, Add1ArgType),
854-
NEONMAP1(vrndxq_v, arm_neon_vrintx, Add1ArgType),
853+
NEONMAP1(vrndx_v, rint, Add1ArgType),
854+
NEONMAP1(vrndxq_v, rint, Add1ArgType),
855855
NEONMAP2(vrshl_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType | UnsignedAlts),
856856
NEONMAP2(vrshlq_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType | UnsignedAlts),
857857
NEONMAP2(vrshr_n_v, arm_neon_vrshiftu, arm_neon_vrshifts, UnsignedAlts),

‎clang/test/CodeGen/arm-neon-directed-rounding.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ float32x4_t test_vrndpq_f32(float32x4_t a) {
216216
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
217217
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
218218
// CHECK-A32-NEXT: [[VRNDX_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
219-
// CHECK-A32-NEXT: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintx.v2f32(<2 x float> [[VRNDX_V_I]])
219+
// CHECK-A32-NEXT: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> [[VRNDX_V_I]])
220220
// CHECK-A32-NEXT: [[VRNDX_V2_I:%.*]] = bitcast <2 x float> [[VRNDX_V1_I]] to <8 x i8>
221221
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDX_V2_I]] to <2 x i32>
222222
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
@@ -241,7 +241,7 @@ float32x2_t test_vrndx_f32(float32x2_t a) {
241241
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
242242
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
243243
// CHECK-A32-NEXT: [[VRNDXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
244-
// CHECK-A32-NEXT: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintx.v4f32(<4 x float> [[VRNDXQ_V_I]])
244+
// CHECK-A32-NEXT: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[VRNDXQ_V_I]])
245245
// CHECK-A32-NEXT: [[VRNDXQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDXQ_V1_I]] to <16 x i8>
246246
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDXQ_V2_I]] to <4 x i32>
247247
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>

‎clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,7 @@ float16x8_t test_vrndpq_f16(float16x8_t a) {
682682
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
683683
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
684684
// CHECK-NEXT: [[VRNDX_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
685-
// CHECK-NEXT: [[VRNDX_V1_I:%.*]] = call <4 x half> @llvm.arm.neon.vrintx.v4f16(<4 x half> [[VRNDX_V_I]])
685+
// CHECK-NEXT: [[VRNDX_V1_I:%.*]] = call <4 x half> @llvm.rint.v4f16(<4 x half> [[VRNDX_V_I]])
686686
// CHECK-NEXT: [[VRNDX_V2_I:%.*]] = bitcast <4 x half> [[VRNDX_V1_I]] to <8 x i8>
687687
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDX_V2_I]] to <4 x i16>
688688
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
@@ -698,7 +698,7 @@ float16x4_t test_vrndx_f16(float16x4_t a) {
698698
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
699699
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
700700
// CHECK-NEXT: [[VRNDXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
701-
// CHECK-NEXT: [[VRNDXQ_V1_I:%.*]] = call <8 x half> @llvm.arm.neon.vrintx.v8f16(<8 x half> [[VRNDXQ_V_I]])
701+
// CHECK-NEXT: [[VRNDXQ_V1_I:%.*]] = call <8 x half> @llvm.rint.v8f16(<8 x half> [[VRNDXQ_V_I]])
702702
// CHECK-NEXT: [[VRNDXQ_V2_I:%.*]] = bitcast <8 x half> [[VRNDXQ_V1_I]] to <16 x i8>
703703
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDXQ_V2_I]] to <8 x i16>
704704
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>

‎llvm/include/llvm/IR/IntrinsicsARM.td‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -679,7 +679,6 @@ def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
679679

680680
// Vector and Scalar Rounding.
681681
def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
682-
def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
683682

684683
// De-interleaving vector loads from N-element structures.
685684
// Source operands are the address and alignment.

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -722,7 +722,8 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
722722
.StartsWith("vrinta.", Intrinsic::round)
723723
.StartsWith("vrintm.", Intrinsic::floor)
724724
.StartsWith("vrintp.", Intrinsic::ceil)
725-
.StartsWith("vrintz", Intrinsic::trunc)
725+
.StartsWith("vrintx.", Intrinsic::rint)
726+
.StartsWith("vrintz.", Intrinsic::trunc)
726727
.Default(Intrinsic::not_intrinsic);
727728
if (ID != Intrinsic::not_intrinsic) {
728729
NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1552,6 +1552,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15521552
setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
15531553
setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
15541554
setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1555+
setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
1556+
setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
15551557
}
15561558

15571559
if (Subtarget->hasFullFP16()) {
@@ -1573,6 +1575,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15731575
setOperationAction(ISD::FCEIL, MVT::v8f16, Legal);
15741576
setOperationAction(ISD::FTRUNC, MVT::v4f16, Legal);
15751577
setOperationAction(ISD::FTRUNC, MVT::v8f16, Legal);
1578+
setOperationAction(ISD::FRINT, MVT::v4f16, Legal);
1579+
setOperationAction(ISD::FRINT, MVT::v8f16, Legal);
15761580
}
15771581
}
15781582

‎llvm/lib/Target/ARM/ARMInstrNEON.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7313,7 +7313,7 @@ multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
73137313
}
73147314

73157315
defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
7316-
defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
7316+
defm VRINTXN : VRINT_FPI<"x", 0b001, frint>;
73177317
defm VRINTAN : VRINT_FPI<"a", 0b010, fround>;
73187318
defm VRINTZN : VRINT_FPI<"z", 0b011, ftrunc>;
73197319
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;

‎llvm/test/CodeGen/ARM/vrint.ll‎

Lines changed: 4 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1770,21 +1770,7 @@ define <4 x half> @frintx_4h(<4 x half> %A) nounwind {
17701770
;
17711771
; CHECK-FP16-LABEL: frintx_4h:
17721772
; CHECK-FP16: @ %bb.0:
1773-
; CHECK-FP16-NEXT: vmovx.f16 s2, s0
1774-
; CHECK-FP16-NEXT: vrintx.f16 s2, s2
1775-
; CHECK-FP16-NEXT: vmov r0, s2
1776-
; CHECK-FP16-NEXT: vrintx.f16 s2, s0
1777-
; CHECK-FP16-NEXT: vmov r1, s2
1778-
; CHECK-FP16-NEXT: vrintx.f16 s2, s1
1779-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
1780-
; CHECK-FP16-NEXT: vrintx.f16 s0, s0
1781-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
1782-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
1783-
; CHECK-FP16-NEXT: vmov r0, s2
1784-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
1785-
; CHECK-FP16-NEXT: vmov r0, s0
1786-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
1787-
; CHECK-FP16-NEXT: vorr d0, d16, d16
1773+
; CHECK-FP16-NEXT: vrintx.f16 d0, d0
17881774
; CHECK-FP16-NEXT: bx lr
17891775
%tmp3 = call <4 x half> @llvm.rint.v4f16(<4 x half> %A)
17901776
ret <4 x half> %tmp3
@@ -1934,35 +1920,7 @@ define <8 x half> @frintx_8h(<8 x half> %A) nounwind {
19341920
;
19351921
; CHECK-FP16-LABEL: frintx_8h:
19361922
; CHECK-FP16: @ %bb.0:
1937-
; CHECK-FP16-NEXT: vmovx.f16 s4, s2
1938-
; CHECK-FP16-NEXT: vrintx.f16 s4, s4
1939-
; CHECK-FP16-NEXT: vmov r0, s4
1940-
; CHECK-FP16-NEXT: vrintx.f16 s4, s2
1941-
; CHECK-FP16-NEXT: vmov r1, s4
1942-
; CHECK-FP16-NEXT: vrintx.f16 s4, s3
1943-
; CHECK-FP16-NEXT: vmov.16 d17[0], r1
1944-
; CHECK-FP16-NEXT: vmov.16 d17[1], r0
1945-
; CHECK-FP16-NEXT: vmov r0, s4
1946-
; CHECK-FP16-NEXT: vmovx.f16 s4, s3
1947-
; CHECK-FP16-NEXT: vrintx.f16 s4, s4
1948-
; CHECK-FP16-NEXT: vmov.16 d17[2], r0
1949-
; CHECK-FP16-NEXT: vmov r0, s4
1950-
; CHECK-FP16-NEXT: vmovx.f16 s4, s0
1951-
; CHECK-FP16-NEXT: vrintx.f16 s4, s4
1952-
; CHECK-FP16-NEXT: vmov.16 d17[3], r0
1953-
; CHECK-FP16-NEXT: vmov r0, s4
1954-
; CHECK-FP16-NEXT: vrintx.f16 s4, s0
1955-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
1956-
; CHECK-FP16-NEXT: vmov r1, s4
1957-
; CHECK-FP16-NEXT: vrintx.f16 s4, s1
1958-
; CHECK-FP16-NEXT: vrintx.f16 s0, s0
1959-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
1960-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
1961-
; CHECK-FP16-NEXT: vmov r0, s4
1962-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
1963-
; CHECK-FP16-NEXT: vmov r0, s0
1964-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
1965-
; CHECK-FP16-NEXT: vorr q0, q8, q8
1923+
; CHECK-FP16-NEXT: vrintx.f16 q0, q0
19661924
; CHECK-FP16-NEXT: bx lr
19671925
%tmp3 = call <8 x half> @llvm.rint.v8f16(<8 x half> %A)
19681926
ret <8 x half> %tmp3
@@ -1988,9 +1946,7 @@ define <2 x float> @frintx_2s(<2 x float> %A) nounwind {
19881946
;
19891947
; CHECK-LABEL: frintx_2s:
19901948
; CHECK: @ %bb.0:
1991-
; CHECK-NEXT: vrintx.f32 s3, s1
1992-
; CHECK-NEXT: vrintx.f32 s2, s0
1993-
; CHECK-NEXT: vmov.f64 d0, d1
1949+
; CHECK-NEXT: vrintx.f32 d0, d0
19941950
; CHECK-NEXT: bx lr
19951951
%tmp3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A)
19961952
ret <2 x float> %tmp3
@@ -2022,11 +1978,7 @@ define <4 x float> @frintx_4s(<4 x float> %A) nounwind {
20221978
;
20231979
; CHECK-LABEL: frintx_4s:
20241980
; CHECK: @ %bb.0:
2025-
; CHECK-NEXT: vrintx.f32 s7, s3
2026-
; CHECK-NEXT: vrintx.f32 s6, s2
2027-
; CHECK-NEXT: vrintx.f32 s5, s1
2028-
; CHECK-NEXT: vrintx.f32 s4, s0
2029-
; CHECK-NEXT: vorr q0, q1, q1
1981+
; CHECK-NEXT: vrintx.f32 q0, q0
20301982
; CHECK-NEXT: bx lr
20311983
%tmp3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A)
20321984
ret <4 x float> %tmp3

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