[AMDGPU] Add post-RA scheduling direction control via target features

Author: harrisonGPU

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -116,7 +116,6 @@ enum Direction {
 } // namespace MISched
 
 LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
-LLVM_ABI extern cl::opt<MISched::Direction> PostRADirection;
 LLVM_ABI extern cl::opt<bool> VerifyScheduling;
 #ifndef NDEBUG
 extern cl::opt<bool> ViewMISchedDAGs;

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -190,7 +190,7 @@ cl::opt<MISched::Direction> PreRADirection(
         clEnumValN(MISched::Bidirectional, "bidirectional",
                    "Force bidirectional pre reg-alloc list scheduling")));
 
-cl::opt<MISched::Direction> PostRADirection(
+static cl::opt<MISched::Direction> PostRADirection(
     "misched-postra-direction", cl::Hidden,
     cl::desc("Post reg-alloc list scheduling direction"),
     cl::init(MISched::Unspecified),
@@ -4336,25 +4336,6 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
     RegionPolicy.OnlyTopDown = false;
   }
 
-  LLVM_DEBUG({
-    const char *DirStr = "default";
-    switch (PostRADirection) {
-    case MISched::TopDown:
-      DirStr = "topdown";
-      break;
-    case MISched::BottomUp:
-      DirStr = "bottomup";
-      break;
-    case MISched::Bidirectional:
-      DirStr = "bidirectional";
-      break;
-    default:;
-    }
-
-    dbgs() << "Post-MI-sched direction (" << MF.getName() << "): " << DirStr
-           << '\n';
-  });
-
   BotIdx = NumRegionInstrs - 1;
   this->NumRegionInstrs = NumRegionInstrs;
 }

llvm/lib/Target/AMDGPU/AMDGPUFeatures.td

@@ -6,6 +6,10 @@
 //
 //===----------------------------------------------------------------------===//
 
+defvar TopDown       = [{ MISched::TopDown }];
+defvar BottomUp      = [{ MISched::BottomUp }];
+defvar Bidirectional = [{ MISched::Bidirectional }];
+
 def FeatureFP64 : SubtargetFeature<"fp64",
   "FP64",
   "true",
@@ -54,3 +58,20 @@ def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
   "Enable promote alloca pass"
 >;
 
+def FeaturePostRATopDown : SubtargetFeature <"postra-top-down",
+ "PostRASchedDirection",
+  TopDown,
+  "Force Post-RA scheduler to run top-down"
+>;
+
+def FeaturePostRABottomUp : SubtargetFeature <"postra-bottom-up",
+  "PostRASchedDirection",
+  BottomUp,
+  "Force Post-RA scheduler to run bottom-up"
+>;
+
+def FeaturePostRABidirectional : SubtargetFeature <"postra-bidirectional",
+  "PostRASchedDirection",
+  Bidirectional,
+  "Force Post-RA scheduler to run bidirectionally"
+>;

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

@@ -15,6 +15,7 @@
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
 
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/Support/Alignment.h"
 #include "llvm/TargetParser/Triple.h"
@@ -80,6 +81,7 @@ class AMDGPUSubtarget {
   unsigned LocalMemorySize = 0;
   unsigned AddressableLocalMemorySize = 0;
   char WavefrontSizeLog2 = 0;
+  MISched::Direction PostRASchedDirection = MISched::TopDown;
 
 public:
   AMDGPUSubtarget(Triple TT);
@@ -382,6 +384,10 @@ class AMDGPUSubtarget {
   AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const;
 
   virtual ~AMDGPUSubtarget() = default;
+
+  MISched::Direction getPostRASchedDirection() const {
+    return PostRASchedDirection;
+  }
 };
 
 } // end namespace llvm

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -460,11 +460,6 @@ static cl::opt<std::string>
                         cl::desc("Select custom AMDGPU scheduling strategy."),
                         cl::Hidden, cl::init(""));
 
-static cl::opt<std::string>
-    AMDGPUPostRADirection("amdgpu-post-ra-direction",
-                          cl::desc("Select custom AMDGPU postRA direction."),
-                          cl::Hidden, cl::init(""));
-
 static cl::opt<bool> EnableRewritePartialRegUses(
     "amdgpu-enable-rewrite-partial-reg-uses",
     cl::desc("Enable rewrite partial reg uses pass"), cl::init(true),
@@ -1158,29 +1153,6 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
 
 ScheduleDAGInstrs *
 GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
-  if (PostRADirection.getNumOccurrences() == 0) {
-    Attribute PostRADirectionAttr =
-        C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction");
-
-    if (PostRADirectionAttr.isValid()) {
-      StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
-      if (PostRADirectionStr == "topdown")
-        PostRADirection = MISched::TopDown;
-      else if (PostRADirectionStr == "bottomup")
-        PostRADirection = MISched::BottomUp;
-      else if (PostRADirectionStr == "bidirectional")
-        PostRADirection = MISched::Bidirectional;
-      else {
-        PostRADirection = MISched::Unspecified;
-        DiagnosticInfoOptimizationFailure Diag(
-            C->MF->getFunction(), C->MF->getFunction().getSubprogram(),
-            Twine("invalid value for postRa direction attribute: '") +
-                PostRADirectionStr);
-        C->MF->getFunction().getContext().diagnose(Diag);
-      }
-    }
-  }
-
   ScheduleDAGMI *DAG =
       new GCNPostScheduleDAGMILive(C, std::make_unique<PostGenericScheduler>(C),
                                    /*RemoveKillFlags=*/true);

llvm/lib/Target/AMDGPU/GCNSubtarget.cpp

@@ -340,6 +340,40 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
     Policy.ShouldTrackLaneMasks = true;
 }
 
+void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                             unsigned NumRegionInstrs) const {
+  switch (getPostRASchedDirection()) {
+  case MISched::TopDown:
+    Policy.OnlyTopDown = true;
+    Policy.OnlyBottomUp = false;
+    break;
+  case MISched::BottomUp:
+    Policy.OnlyTopDown = false;
+    Policy.OnlyBottomUp = true;
+    break;
+  case MISched::Bidirectional:
+  default:
+    Policy.OnlyTopDown = false;
+    Policy.OnlyBottomUp = false;
+    break;
+  }
+
+  LLVM_DEBUG({
+    const char *DirStr = "topdown";
+    switch (getPostRASchedDirection()) {
+    case MISched::BottomUp:
+      DirStr = "bottomup";
+      break;
+    case MISched::Bidirectional:
+      DirStr = "bidirectional";
+      break;
+    default:
+      break;
+    }
+    dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
+  });
+}
+
 void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
   if (isWave32()) {
     // Fix implicit $vcc operands after MIParser has verified that they match

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -1041,6 +1041,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
                            const SchedRegion &Region) const override;
 
+  void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                 unsigned NumRegionInstrs) const override;
+
   void mirFileLoaded(MachineFunction &MF) const override;
 
   unsigned getMaxNumUserSGPRs() const {

llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll

@@ -0,0 +1,25 @@
+; REQUIRES: asserts
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s
+
+; CHECK: Post-MI-sched direction: topdown
+define float @postra-sched-topdown(float %input) nounwind #0 {
+  %x = fadd float %input, 1.000000e+00
+  ret float %x
+}
+
+; CHECK: Post-MI-sched direction: bottomup
+define float @postra-sched-bottomup(float %input) nounwind #1 {
+  %x = fsub float %input, 1.000000e+00
+  ret float %x
+}
+
+; CHECK: Post-MI-sched direction: bidirectional
+define float @postra-sched-bidirectional(float %input) nounwind #2 {
+  %x = fadd float %input, 1.000000e+00
+  ret float %x
+}
+
+attributes #0 = { "target-features"="+postra-top-down" }
+attributes #1 = { "target-features"="+postra-bottom-up" }
+attributes #2 = { "target-features"="+postra-bidirectional" }