Skip call args for all calls

Author: rovka

llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

@@ -146,13 +146,7 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
                                           /*IncludeCalls=*/false);
 
   // A tail call isn't considered a call for MachineFrameInfo's purposes.
-  bool HasCalls = FrameInfo.hasCalls() || FrameInfo.hasTailCall();
-  // Functions that use the llvm.amdgcn.init.whole.wave intrinsic often have
-  // VGPR arguments that are only added for the purpose of preserving the
-  // inactive lanes. These should not be included in the number of used VGPRs.
-  bool NeedsExplicitVGPRCount = MFI->hasInitWholeWave();
-  if (!HasCalls && !NeedsExplicitVGPRCount) {
-
+  if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
     Info.NumVGPR = TRI.getNumUsedPhysRegs(MRI, AMDGPU::VGPR_32RegClass,
                                           /*IncludeCalls=*/false);
     return Info;
@@ -163,34 +157,24 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
 
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
-      if (NeedsExplicitVGPRCount) {
-        for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
-          const MachineOperand &MO = MI.getOperand(I);
-
-          if (!MO.isReg())
-            continue;
-          Register Reg = MO.getReg();
-          const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(Reg);
-
-          if (!RC || !TRI.isVGPRClass(RC))
-            continue;
-
-          // Skip inactive VGPRs in chain functions with the init.whole.wave
-          // intrinsic. These will only appear as implicit use operands on the
-          // chain call, and as the def of an IMPLICIT_DEF. We're going to skip
-          // implicit defs unconditionally though because if they're important
-          // in a different context then they will be counted when they are
-          // used.
-          bool IsChainCall =
-              MFI->isChainFunction() && MI.getOpcode() == AMDGPU::SI_TCRETURN;
-          if (IsChainCall || MI.isImplicitDef())
-            continue;
-
-          unsigned Width = divideCeil(TRI.getRegSizeInBits(*RC), 32);
-          unsigned HWReg = TRI.getHWRegIndex(Reg);
-          int MaxUsed = HWReg + Width - 1;
-          MaxVGPR = std::max(MaxUsed, MaxVGPR);
-        }
+      for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
+        const MachineOperand &MO = MI.getOperand(I);
+
+        if (!MO.isReg())
+          continue;
+        Register Reg = MO.getReg();
+        const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(Reg);
+
+        if (!RC || !TRI.isVGPRClass(RC))
+          continue;
+
+        if (MI.isCall() || MI.isImplicitDef())
+          continue;
+
+        unsigned Width = divideCeil(TRI.getRegSizeInBits(*RC), 32);
+        unsigned HWReg = TRI.getHWRegIndex(Reg);
+        int MaxUsed = HWReg + Width - 1;
+        MaxVGPR = std::max(MaxUsed, MaxVGPR);
       }
 
       if (MI.isCall()) {
@@ -252,10 +236,7 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
     }
   }
 
-  if (NeedsExplicitVGPRCount)
-    Info.NumVGPR = MaxVGPR + 1;
-  else
-    Info.NumVGPR = TRI.getNumUsedPhysRegs(MRI, AMDGPU::VGPR_32RegClass, false);
+  Info.NumVGPR = MaxVGPR + 1;
 
   return Info;
 }

llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll

@@ -16,7 +16,7 @@ entry:
 }
 
 ; CHECK-LABEL: __unnamed_2:
-; CHECK: .set __unnamed_2.num_vgpr, max(32, __unnamed_1.num_vgpr)
+; CHECK: .set __unnamed_2.num_vgpr, max(1, __unnamed_1.num_vgpr)
 ; CHECK: .set __unnamed_2.num_agpr, max(0, __unnamed_1.num_agpr)
 ; CHECK: .set __unnamed_2.numbered_sgpr, max(34, __unnamed_1.numbered_sgpr)
 ; CHECK: .set __unnamed_2.private_seg_size, 16+max(__unnamed_1.private_seg_size)

llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll

@@ -1264,9 +1264,9 @@ define amdgpu_kernel void @k1024_call_no_agprs_ub_callee() #1025 {
 }
 
 ; GCN-LABEL: {{^}}f1024_0:
-; GFX90A: NumVgprs: 32
+; GFX90A: NumVgprs: 1
 ; GFX90A: NumAgprs: 1
-; GFX90A: TotalNumVgprs: 33
+; GFX90A: TotalNumVgprs: 5
 define void @f1024_0() #1024 {
   call void @foo()
   ret void

llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll

@@ -0,0 +1,27 @@
+; RUN: llc -mcpu=gfx1200 -o - < %s | FileCheck %s
+; Check that reads of a VGPR in kernels counts towards VGPR count, but in functions, only writes of VGPRs count towards VGPR count.
+target triple = "amdgcn--amdpal"
+
+@global = addrspace(1) global i32 poison, align 4
+
+; CHECK-LABEL: amdpal.pipelines:
+
+; Shouldn't report the part of %vgpr_args that's not used
+; CHECK-LABEL: entry_point_symbol: cs_calling_chain
+; CHECK: .vgpr_count:     0xa
+define amdgpu_cs void @cs_calling_chain(i32 %vgpr, i32 inreg %sgpr) {
+  %vgpr_args = insertvalue {i32, i32, i32, i32} poison, i32 %vgpr, 1
+  call void (ptr, i32, i32, {i32, i32, i32, i32}, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.i32.s(
+    ptr @chain_func, i32 0, i32 inreg %sgpr, {i32, i32, i32, i32} %vgpr_args, i32 0)
+  unreachable
+}
+
+; Neither uses not writes a VGPR
+; CHECK-LABEL: chain_func:
+; CHECK: .vgpr_count:     0x1
+define amdgpu_cs_chain void @chain_func([32 x i32] %args) {
+entry:
+  call void (ptr, i32, {}, [32 x i32], i32, ...) @llvm.amdgcn.cs.chain.p0.i32.s.a(
+        ptr @chain_func, i32 0, {} inreg {}, [32 x i32] %args, i32 0)
+  unreachable
+}

llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll

@@ -16,16 +16,6 @@ entry:
   ret void
 }
 
-; Neither uses not writes a VGPR
-; CHECK-LABEL: chain_func:
-; CHECK: .vgpr_count:     0x28
-define amdgpu_cs_chain void @chain_func([32 x i32] %args) {
-entry:
-  call void (ptr, i32, {}, [32 x i32], i32, ...) @llvm.amdgcn.cs.chain.p0.i32.s.a(
-        ptr @chain_func, i32 0, {} inreg {}, [32 x i32] %args, i32 0)
-  unreachable
-}
-
 ; Neither uses not writes a VGPR
 ; CHECK-LABEL: gfx_func:
 ; CHECK: .vgpr_count:     0x20