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mikhailramalhomikhailramalho
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[RISCV][VLOPT] Add support for vrgather (#148249)
This PR adds support for the vrgather.vi, vrgather.vx, vrgather.vv, vrgatherei16.vv instructions in the RISC-V VLOptimizer. To support vrgatherei16.vv I also needed to add support for it in getOperandLog2EEW.
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‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -747,6 +747,14 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
747747
return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
748748
}
749749

750+
// Vector Register Gather with 16-bit Index Elements Instruction
751+
// Dest and source data EEW=SEW. Index vector EEW=16.
752+
case RISCV::VRGATHEREI16_VV: {
753+
if (MO.getOperandNo() == 2)
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return 4;
755+
return MILog2SEW;
756+
}
757+
750758
default:
751759
return std::nullopt;
752760
}
@@ -1058,6 +1066,11 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10581066
case RISCV::VSLIDEDOWN_VI:
10591067
case RISCV::VSLIDE1UP_VX:
10601068
case RISCV::VFSLIDE1UP_VF:
1069+
// Vector Register Gather Instructions
1070+
case RISCV::VRGATHER_VI:
1071+
case RISCV::VRGATHER_VV:
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case RISCV::VRGATHER_VX:
1073+
case RISCV::VRGATHEREI16_VV:
10611074
// Vector Single-Width Floating-Point Add/Subtract Instructions
10621075
case RISCV::VFADD_VF:
10631076
case RISCV::VFADD_VV:

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5468,9 +5468,8 @@ define <vscale x 4 x i32> @vrgather_vi(<vscale x 4 x i32> %a, <vscale x 4 x i32>
54685468
;
54695469
; VLOPT-LABEL: vrgather_vi:
54705470
; VLOPT: # %bb.0:
5471-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
5472-
; VLOPT-NEXT: vrgather.vi v12, v8, 5
54735471
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
5472+
; VLOPT-NEXT: vrgather.vi v12, v8, 5
54745473
; VLOPT-NEXT: vadd.vv v8, v12, v10
54755474
; VLOPT-NEXT: ret
54765475
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)
@@ -5489,9 +5488,8 @@ define <vscale x 4 x i32> @vrgather_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32>
54895488
;
54905489
; VLOPT-LABEL: vrgather_vv:
54915490
; VLOPT: # %bb.0:
5492-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
5493-
; VLOPT-NEXT: vrgather.vv v12, v8, v10
54945491
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
5492+
; VLOPT-NEXT: vrgather.vv v12, v8, v10
54955493
; VLOPT-NEXT: vadd.vv v8, v12, v8
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; VLOPT-NEXT: ret
54975495
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %idx, iXLen -1)
@@ -5510,9 +5508,8 @@ define <vscale x 4 x i32> @vrgather_vx(<vscale x 4 x i32> %a, iXLen %idx, <vscal
55105508
;
55115509
; VLOPT-LABEL: vrgather_vx:
55125510
; VLOPT: # %bb.0:
5513-
; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
5514-
; VLOPT-NEXT: vrgather.vx v12, v8, a0
55155511
; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
5512+
; VLOPT-NEXT: vrgather.vx v12, v8, a0
55165513
; VLOPT-NEXT: vadd.vv v8, v12, v10
55175514
; VLOPT-NEXT: ret
55185515
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %idx, iXLen -1)
@@ -5531,9 +5528,8 @@ define <vscale x 4 x i32> @vrgatherei16_vv(<vscale x 4 x i32> %a, <vscale x 4 x
55315528
;
55325529
; VLOPT-LABEL: vrgatherei16_vv:
55335530
; VLOPT: # %bb.0:
5534-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
5535-
; VLOPT-NEXT: vrgatherei16.vv v12, v8, v10
55365531
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
5532+
; VLOPT-NEXT: vrgatherei16.vv v12, v8, v10
55375533
; VLOPT-NEXT: vadd.vv v8, v12, v8
55385534
; VLOPT-NEXT: ret
55395535
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i16> %idx, iXLen -1)

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1801,4 +1801,63 @@ body: |
18011801
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */
18021802
%x:vr = PseudoVMSET_M_B8 -1, 0
18031803
%y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0
1804+
...
1805+
---
1806+
name: vrgatherei16_vv
1807+
body: |
1808+
bb.0:
1809+
; CHECK-LABEL: name: vrgatherei16_vv
1810+
; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
1811+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
1812+
%x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0
1813+
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
1814+
...
1815+
---
1816+
name: vrgatherei16_vv_incompatible_data_eew
1817+
body: |
1818+
bb.0:
1819+
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_data_eew
1820+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
1821+
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
1822+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
1823+
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
1824+
...
18041825
---
1826+
name: vrgatherei16_vv_incompatible_index_eew
1827+
body: |
1828+
bb.0:
1829+
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_eew
1830+
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
1831+
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */
1832+
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
1833+
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0
1834+
...
1835+
---
1836+
name: vrgatherei16_vv_incompatible_dest_emul
1837+
body: |
1838+
bb.0:
1839+
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_dest_emul
1840+
; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
1841+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
1842+
%x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0
1843+
%y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
1844+
...
1845+
---
1846+
name: vrgatherei16_vv_incompatible_source_emul
1847+
body: |
1848+
bb.0:
1849+
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_source_emul
1850+
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
1851+
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
1852+
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0
1853+
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
1854+
...
1855+
---
1856+
name: vrgatherei16_vv_incompatible_index_emul
1857+
body: |
1858+
bb.0:
1859+
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_emul
1860+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
1861+
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */
1862+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
1863+
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0

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