i8

Author: linuxrocks123

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -5580,8 +5580,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
   /// \param N Node to expand
   /// \param IsNegative indicate negated abs
   /// \returns The expansion result or SDValue() if it fails.
-  SDValue expandABS(SDNode *N, SelectionDAG &DAG,
-                    bool IsNegative = false) const;
+  virtual SDValue expandABS(SDNode *N, SelectionDAG &DAG,
+                            bool IsNegative = false) const;
 
   /// Expand ABDS/ABDU nodes. Expands vector/scalar ABDS/ABDU nodes.
   /// \param N Node to expand

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -5286,6 +5286,28 @@ SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
   return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
 }
 
+SDValue AMDGPUTargetLowering::expandABS(SDNode *N, SelectionDAG &DAG,
+                                        bool IsNegative) const {
+  if (N->isDivergent() ||
+      (N->getValueType(0) != MVT::i8 && N->getValueType(0) != MVT::i16))
+    return TargetLowering::expandABS(N, DAG, IsNegative);
+
+  //(abs i8/i16 (i8/i16 op1)) -> (trunc i8/i16 (abs i32 (sext i32 (i8/i16
+  // op1))))
+  SDValue Src = N->getOperand(0);
+  SDLoc DL(Src);
+  SDValue SExtSrc = DAG.getSExtOrTrunc(Src, DL, MVT::i32);
+  SDValue ExtAbs = DAG.getNode(ISD::ABS, DL, MVT::i32, SExtSrc);
+  SDValue TruncResult =
+      DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), ExtAbs);
+
+  if (!IsNegative)
+    return TruncResult;
+
+  return DAG.getNode(ISD::SUB, DL, N->getValueType(0),
+                     DAG.getConstant(0, DL, N->getValueType(0)), TruncResult);
+}
+
 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
                                                 DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

@@ -45,6 +45,9 @@ class AMDGPUTargetLowering : public TargetLowering {
   /// original size will not change the value.
   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
 
+  virtual SDValue expandABS(SDNode *N, SelectionDAG &DAG,
+                            bool IsNegative = false) const override;
+
 protected:
   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -178,10 +178,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
     addRegisterClass(MVT::v32i16, &AMDGPU::SGPR_512RegClass);
     addRegisterClass(MVT::v32f16, &AMDGPU::SGPR_512RegClass);
     addRegisterClass(MVT::v32bf16, &AMDGPU::SGPR_512RegClass);
-
-    // We don't want the default expansion of 16-bit ABS since we can
-    // sign-extend and use the 32-bit ABS operation for 16-bit ABS with SGPRs
-    setOperationAction(ISD::ABS, MVT::i16, Custom);
   }
 
   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
@@ -6779,9 +6775,6 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::DEBUGTRAP:
     return lowerDEBUGTRAP(Op, DAG);
   case ISD::ABS:
-    if (Op.getValueType() == MVT::i16)
-      return lowerABSi16(Op, DAG);
-    LLVM_FALLTHROUGH;
   case ISD::FABS:
   case ISD::FNEG:
   case ISD::FCANONICALIZE:
@@ -8147,25 +8140,6 @@ SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
   return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
 }
 
-// sign-extend and use the 32-bit ABS operation for 16-bit ABS with SGPRs
-SDValue SITargetLowering::lowerABSi16(SDValue Op, SelectionDAG &DAG) const {
-  assert(Op.getOpcode() == ISD::ABS &&
-         "Tried to select abs with non-abs opcode.");
-  assert(Op.getValueType() == MVT::i16 &&
-         "Tried to select abs i16 lowering with non-i16 type.");
-
-  // Divergent operands will not end up using SGPRs.
-  if (Op->isDivergent())
-    return SDValue();
-
-  //(abs i16 (i16 op1)) -> (trunc i16 (abs i32 (sext i32 (i16 op1))))
-  SDValue Src = Op.getOperand(0);
-  SDLoc DL(Src);
-  SDValue SExtSrc = DAG.getSExtOrTrunc(Src, DL, MVT::i32);
-  SDValue ExtAbs = DAG.getNode(ISD::ABS, DL, MVT::i32, SExtSrc);
-  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, ExtAbs);
-}
-
 SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
                                              SelectionDAG &DAG) const {
   if (Subtarget->hasApertureRegs()) {

llvm/lib/Target/AMDGPU/SIISelLowering.h

@@ -184,7 +184,6 @@ class SITargetLowering final : public AMDGPUTargetLowering {
   SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
-  SDValue lowerABSi16(SDValue Op, SelectionDAG &DAG) const;
 
   SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
 

llvm/test/CodeGen/AMDGPU/llvm.abs.ll

@@ -17,6 +17,17 @@ declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
 declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
 declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
 
+define amdgpu_cs i8 @abs_sgpr_i8(i8 inreg %arg) {
+  %res = call i8 @llvm.abs.i8(i8 %arg, i1 false)
+  ret i8 %res
+}
+
+define amdgpu_cs i8 @abs_sgpr_i8_neg(i8 inreg %arg) {
+  %res1 = call i8 @llvm.abs.i8(i8 %arg, i1 false)
+  %res2 = sub i8 0, %res1
+  ret i8 %res2
+}
+
 define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
 ; SDAG6-LABEL: abs_sgpr_i16:
 ; SDAG6:       ; %bb.0: