Assume machineverifier will handle the cases where the register

size is incorrect. In that case, a copy from physical reg to VCC
is allowed.

Author: Jun Wang

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -119,34 +119,6 @@ bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
          RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
 }
 
-// Returns true if this is a copy from physical reg to VCC.
-// The parameter IsValid further indicates if the copy is valid.
-bool AMDGPUInstructionSelector::isCopyPhysicalToVCC(
-    Register DstReg, Register SrcReg, const MachineRegisterInfo &MRI,
-    bool &IsValid) const {
-  if (DstReg.isPhysical())
-    return false;
-  if (!SrcReg.isPhysical() || SrcReg == AMDGPU::SCC)
-    return false;
-
-  auto &RegClassOrBank = MRI.getRegClassOrRegBank(DstReg);
-  const TargetRegisterClass *RC =
-      RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
-  if (RC) {
-    const LLT Ty = MRI.getType(DstReg);
-    if (!Ty.isValid() || Ty.getSizeInBits() != 1)
-      return false;
-    // G_TRUNC s1 result is never vcc.
-    if (MRI.getVRegDef(DstReg)->getOpcode() == AMDGPU::G_TRUNC ||
-        !RC->hasSuperClassEq(TRI.getBoolRC()))
-      return false;
-    IsValid = RC->contains(SrcReg);
-    return true;
-  }
-
-  return false;
-}
-
 bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   const DebugLoc &DL = I.getDebugLoc();
   MachineBasicBlock *BB = I.getParent();
@@ -157,10 +129,6 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   Register DstReg = Dst.getReg();
   Register SrcReg = Src.getReg();
 
-  bool validPhyToRCC = false;
-  if (isCopyPhysicalToVCC(DstReg, SrcReg, *MRI, validPhyToRCC))
-    return validPhyToRCC;
-
   if (isVCC(DstReg, *MRI)) {
     if (SrcReg == AMDGPU::SCC) {
       const TargetRegisterClass *RC
@@ -170,6 +138,10 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
       return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
     }
 
+    // Allow copy from physical register other than SCC to s1.
+    if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC)
+      return true;
+
     if (!isVCC(SrcReg, *MRI)) {
       // TODO: Should probably leave the copy and let copyPhysReg expand it.
       if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

@@ -73,8 +73,6 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
 
   bool isInstrUniform(const MachineInstr &MI) const;
   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
-  bool isCopyPhysicalToVCC(Register DstReg, Register SrcReg,
-                           const MachineRegisterInfo &MRI, bool &IsValid) const;
 
   const RegisterBank *getArtifactRegBank(
     Register Reg, const MachineRegisterInfo &MRI,