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davemgreendavemgreen
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[AArch64] Convert aarch64_neon_sqxtn to ISD::TRUNCATE_SSAT_S and replace tablegen patterns
This lowers the aarch64_neon_sqxtn intrinsics to the new TRUNCATE_SSAT_S ISD nodes, performing the same for sqxtun and uqxtn. This allows us to clean up the tablegen patterns a little and in a future commit add combines for sqxtn.
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2 files changed

+12
-82
lines changed

2 files changed

+12
-82
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5941,6 +5941,15 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
59415941
Op.getOperand(1))));
59425942
return SDValue();
59435943
}
5944+
case Intrinsic::aarch64_neon_sqxtn:
5945+
return DAG.getNode(ISD::TRUNCATE_SSAT_S, dl, Op.getValueType(),
5946+
Op.getOperand(1));
5947+
case Intrinsic::aarch64_neon_sqxtun:
5948+
return DAG.getNode(ISD::TRUNCATE_SSAT_U, dl, Op.getValueType(),
5949+
Op.getOperand(1));
5950+
case Intrinsic::aarch64_neon_uqxtn:
5951+
return DAG.getNode(ISD::TRUNCATE_USAT_U, dl, Op.getValueType(),
5952+
Op.getOperand(1));
59445953
case Intrinsic::aarch64_sve_whilelo:
59455954
return optimizeIncrementingWhile(Op, DAG, /*IsSigned=*/false,
59465955
/*IsEqual=*/false);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 3 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -5430,14 +5430,14 @@ defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", any_sint_to_fp>;
54305430
defm SHLL : SIMDVectorLShiftLongBySizeBHS;
54315431
defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
54325432
defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
5433-
defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
5434-
defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
5433+
defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", truncssat_s>;
5434+
defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", truncssat_u>;
54355435
defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
54365436
defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
54375437
BinOpFrag<(add node:$LHS, (AArch64uaddlp node:$RHS))> >;
54385438
defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp", AArch64uaddlp>;
54395439
defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", any_uint_to_fp>;
5440-
defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
5440+
defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", truncusat_u>;
54415441
defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
54425442
defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
54435443
defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
@@ -5476,85 +5476,6 @@ defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
54765476
defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
54775477
defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
54785478

5479-
// Constant vector values, used in the S/UQXTN patterns below.
5480-
def VImmFF: PatLeaf<(AArch64NvCast (v2i64 (AArch64movi_edit (i32 85))))>;
5481-
def VImmFFFF: PatLeaf<(AArch64NvCast (v2i64 (AArch64movi_edit (i32 51))))>;
5482-
def VImm7F: PatLeaf<(AArch64movi_shift (i32 127), (i32 0))>;
5483-
def VImm80: PatLeaf<(AArch64mvni_shift (i32 127), (i32 0))>;
5484-
def VImm7FFF: PatLeaf<(AArch64movi_msl (i32 127), (i32 264))>;
5485-
def VImm8000: PatLeaf<(AArch64mvni_msl (i32 127), (i32 264))>;
5486-
5487-
// trunc(umin(X, 255)) -> UQXTRN v8i8
5488-
def : Pat<(v8i8 (truncusat_u (v8i16 V128:$Vn))),
5489-
(UQXTNv8i8 V128:$Vn)>;
5490-
// trunc(umin(X, 65535)) -> UQXTRN v4i16
5491-
def : Pat<(v4i16 (truncusat_u (v4i32 V128:$Vn))),
5492-
(UQXTNv4i16 V128:$Vn)>;
5493-
// trunc(umin(X, 4294967295)) -> UQXTRN v2i32
5494-
def : Pat<(v2i32 (truncusat_u (v2i64 V128:$Vn))),
5495-
(UQXTNv2i32 V128:$Vn)>;
5496-
// trunc(smin(smax(X, -128), 128)) -> SQXTRN
5497-
def : Pat<(v8i8 (truncssat_s (v8i16 V128:$Vn))),
5498-
(SQXTNv8i8 V128:$Vn)>;
5499-
// trunc(smin(smax(X, -32768), 32767)) -> SQXTRN
5500-
def : Pat<(v4i16 (truncssat_s (v4i32 V128:$Vn))),
5501-
(SQXTNv4i16 V128:$Vn)>;
5502-
// trunc(smin(smax(X, -2147483648), 2147483647)) -> SQXTRN
5503-
def : Pat<(v2i32 (truncssat_s (v2i64 V128:$Vn))),
5504-
(SQXTNv2i32 V128:$Vn)>;
5505-
// trunc(umin(smax(X, 0), 255)) -> SQXTUN
5506-
def : Pat<(v8i8 (truncssat_u (v8i16 V128:$Vn))),
5507-
(SQXTUNv8i8 V128:$Vn)>;
5508-
// trunc(umin(smax(X, 0), 65535)) -> SQXTUN
5509-
def : Pat<(v4i16 (truncssat_u (v4i32 V128:$Vn))),
5510-
(SQXTUNv4i16 V128:$Vn)>;
5511-
// trunc(umin(smax(X, 0), 4294967295)) -> SQXTUN
5512-
def : Pat<(v2i32 (truncssat_u (v2i64 V128:$Vn))),
5513-
(SQXTUNv2i32 V128:$Vn)>;
5514-
5515-
// truncusat_u
5516-
// concat_vectors(Vd, truncusat_u(Vn)) ~> UQXTRN(Vd, Vn)
5517-
def : Pat<(v16i8 (concat_vectors
5518-
(v8i8 V64:$Vd),
5519-
(v8i8 (truncusat_u (v8i16 V128:$Vn))))),
5520-
(UQXTNv16i8 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5521-
def : Pat<(v8i16 (concat_vectors
5522-
(v4i16 V64:$Vd),
5523-
(v4i16 (truncusat_u (v4i32 V128:$Vn))))),
5524-
(UQXTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5525-
def : Pat<(v4i32 (concat_vectors
5526-
(v2i32 V64:$Vd),
5527-
(v2i32 (truncusat_u (v2i64 V128:$Vn))))),
5528-
(UQXTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5529-
5530-
// concat_vectors(Vd, truncssat_s(Vn)) ~> SQXTN2(Vd, Vn)
5531-
def : Pat<(v16i8 (concat_vectors
5532-
(v8i8 V64:$Vd),
5533-
(v8i8 (truncssat_s (v8i16 V128:$Vn))))),
5534-
(SQXTNv16i8 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5535-
def : Pat<(v8i16 (concat_vectors
5536-
(v4i16 V64:$Vd),
5537-
(v4i16 (truncssat_s (v4i32 V128:$Vn))))),
5538-
(SQXTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5539-
def : Pat<(v4i32 (concat_vectors
5540-
(v2i32 V64:$Vd),
5541-
(v2i32 (truncssat_s (v2i64 V128:$Vn))))),
5542-
(SQXTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5543-
5544-
// concat_vectors(Vd, truncssat_u(Vn)) ~> SQXTUN2(Vd, Vn)
5545-
def : Pat<(v16i8 (concat_vectors
5546-
(v8i8 V64:$Vd),
5547-
(v8i8 (truncssat_u (v8i16 V128:$Vn))))),
5548-
(SQXTUNv16i8 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5549-
def : Pat<(v8i16 (concat_vectors
5550-
(v4i16 V64:$Vd),
5551-
(v4i16 (truncssat_u (v4i32 V128:$Vn))))),
5552-
(SQXTUNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5553-
def : Pat<(v4i32 (concat_vectors
5554-
(v2i32 V64:$Vd),
5555-
(v2i32 (truncssat_u (v2i64 V128:$Vn))))),
5556-
(SQXTUNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn)>;
5557-
55585479
// Select BSWAP vector instructions into REV instructions
55595480
def : Pat<(v4i16 (bswap (v4i16 V64:$Rn))),
55605481
(v4i16 (REV16v8i8 (v4i16 V64:$Rn)))>;

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