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AMDGPU: Use Register type for isStackAccess (#154320)
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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9229,7 +9229,7 @@ bool SIInstrInfo::isHighLatencyDef(int Opc) const {
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(isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc) || isFLAT(Opc));
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}
92319231

9232-
unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
9232+
Register SIInstrInfo::isStackAccess(const MachineInstr &MI,
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int &FrameIndex) const {
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const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
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if (!Addr || !Addr->isFI())
@@ -9242,7 +9242,7 @@ unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
92429242
return getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
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}
92449244

9245-
unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
9245+
Register SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
92469246
int &FrameIndex) const {
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const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
92489248
assert(Addr && Addr->isFI());

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1407,8 +1407,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
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return get(pseudoToMCOpcode(Opcode));
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}
14091409

1410-
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1411-
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1410+
Register isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1411+
Register isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
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14131413
Register isLoadFromStackSlot(const MachineInstr &MI,
14141414
int &FrameIndex) const override;

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