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[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)
This extension adds two external input output instructions for non-memory-mapped device. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <[email protected]>
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -206,6 +206,7 @@
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension)
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// CHECK-NEXT: xqciio 0.1 'Xqciio' (Qualcomm uC External Input Output Extension)
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// CHECK-NEXT: xqcilb 0.2 'Xqcilb' (Qualcomm uC Long Branch Extension)
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// CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension)
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// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)

‎llvm/docs/RISCVUsage.rst‎

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@@ -461,6 +461,9 @@ The current vendor extensions supported are:
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``experimental-Xqcicsr``
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LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqciio``
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LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqciint``
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LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -142,6 +142,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcisync` (Sync Delay)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqciio` (External Input Output)
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extension.
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* Adds assembler support for the 'Zilsd` (Load/Store Pair Instructions)
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extension.
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* Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -844,6 +844,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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bool isUImm9Lsb000() const { return isUImmShifted<6, 3>(); }
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bool isUImm14Lsb00() const { return isUImmShifted<12, 2>(); }
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bool isUImm10Lsb00NonZero() const {
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return isUImmPred(
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[](int64_t Imm) { return isShiftedUInt<8, 2>(Imm) && (Imm != 0); });
@@ -1521,6 +1523,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 10) - 1);
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case Match_InvalidUImm11:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
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case Match_InvalidUImm14Lsb00:
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return generateImmOutOfRangeError(
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Operands, ErrorInfo, 0, (1 << 14) - 4,
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"immediate must be a multiple of 4 bytes in the range");
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case Match_InvalidUImm16NonZero:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 16) - 1);
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case Match_InvalidSImm12:

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -671,15 +671,15 @@ static constexpr FeatureBitset XRivosFeatureGroup = {
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};
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static constexpr FeatureBitset XqciFeatureGroup = {
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RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
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RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
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RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
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RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
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RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
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RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
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RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
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RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
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RISCV::FeatureVendorXqcisync,
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RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
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RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
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RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
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RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
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RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
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RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
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RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
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RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
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RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
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};
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static constexpr FeatureBitset XSfVectorGroup = {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

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@@ -314,6 +314,7 @@ enum OperandType : unsigned {
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OPERAND_UIMM10_LSB00_NONZERO,
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OPERAND_UIMM11,
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OPERAND_UIMM12,
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OPERAND_UIMM14_LSB00,
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OPERAND_UIMM16,
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OPERAND_UIMM16_NONZERO,
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OPERAND_UIMM20,

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1376,6 +1376,13 @@ def HasVendorXqcicm
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AssemblerPredicate<(all_of FeatureVendorXqcicm),
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"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
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def FeatureVendorXqciio
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: RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">;
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def HasVendorXqciio
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: Predicate<"Subtarget->hasVendorXqciio()">,
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AssemblerPredicate<(all_of FeatureVendorXqciio),
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"'Xqciio' (Qualcomm uC External Input Output Extension)">;
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def FeatureVendorXqciint
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: RISCVExperimentalExtension<0, 4, "Qualcomm uC Interrupts Extension",
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[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -69,6 +69,15 @@ def uimm10 : RISCVUImmLeafOp<10>;
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def uimm11 : RISCVUImmLeafOp<11>;
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// A 14-bit unsigned immediate where the least significant two bits are zero.
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def uimm14lsb00 : RISCVOp,
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ImmLeaf<XLenVT, [{return isShiftedUInt<12, 2>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<14, "Lsb00">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmOperand<14>";
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let OperandType = "OPERAND_UIMM14_LSB00";
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}
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def uimm16nonzero : RISCVOp<XLenVT>,
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ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<16>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<16, "NonZero">;
@@ -742,6 +751,28 @@ def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
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} // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
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let Predicates = [HasVendorXqciio, IsRV32] in {
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
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def QC_OUTW : RVInstI<0b100, OPC_CUSTOM_0, (outs),
757+
(ins GPR:$rs2, GPR:$rs1, uimm14lsb00:$imm14),
758+
"qc.outw", "$rs2, ${imm14}(${rs1})"> {
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bits<5> rs2;
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bits<14> imm14;
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762+
let rd = rs2;
763+
let imm12 = imm14{13-2};
764+
}
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def QC_INW : RVInstI<0b101, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
767+
(ins GPR:$rs1, uimm14lsb00:$imm14),
768+
"qc.inw", "$rd, ${imm14}(${rs1})"> {
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bits<14> imm14;
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771+
let imm12 = imm14{13-2};
772+
}
773+
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
774+
} // Predicates = [HasVendorXqciio, IsRV32]
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let Predicates = [HasVendorXqcilo, IsRV32] in {
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def QC_E_LB : QCIRVInstEILoad<0b101, 0b00, "qc.e.lb">;
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def QC_E_LBU : QCIRVInstEILoad<0b101, 0b01, "qc.e.lbu">;
@@ -859,6 +890,15 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
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// Aliases
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXqciio, IsRV32] in {
894+
let EmitPriority = 0 in {
895+
def : InstAlias<"qc.outw $rs2, (${rs1})",
896+
(QC_OUTW GPR:$rs2, GPR:$rs1, 0)>;
897+
def : InstAlias<"qc.inw $rd, (${rs1})",
898+
(QC_INW GPRNoX0:$rd, GPR:$rs1, 0)>;
899+
} // EmitPriority = 0
900+
} // Predicates = [HasVendorXqciio, IsRV32]
901+
862902
let Predicates = [HasVendorXqcilsm, IsRV32] in {
863903
let EmitPriority = 0 in {
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def : InstAlias<"qc.swm $rs3, $rs2, (${rs1})",

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -745,9 +745,9 @@ Error RISCVISAInfo::checkDependency() {
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746746
static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"}, {"xqcicli"},
748-
{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilb"},
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{"xqcili"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"},
750-
{"xqcisls"}, {"xqcisync"}};
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{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqciio"},
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{"xqcilb"}, {"xqcili"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"},
750+
{"xqcisim"}, {"xqcisls"}, {"xqcisync"}};
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static constexpr StringLiteral ZcdOverlaps[] = {
752752
{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
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‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -94,6 +94,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciio %s -o - | FileCheck --check-prefix=RV32XQCIIO %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilb %s -o - | FileCheck --check-prefix=RV32XQCILB %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcili %s -o - | FileCheck --check-prefix=RV32XQCILI %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
@@ -431,6 +432,7 @@
431432
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
432433
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4"
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; RV32XQCIIO: .attribute 5, "rv32i2p1_xqciio0p1"
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; RV32XQCILB: .attribute 5, "rv32i2p1_zca1p0_xqcilb0p2"
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; RV32XQCILI: .attribute 5, "rv32i2p1_zca1p0_xqcili0p2"
436438
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"

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