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Enable dead register definitions at O0
This is because the assembler/disassembler will otherwise show this as an adds or subs and not cmp or cmn. Even gcc does this. And, this is just allocating register to 0 reg. Will this optimize -O0? Well, minimally it will put less register pressure maybe, but that is not the point. The point is that it should resolve to aliases for better understanding, which is why -O0 exists to begin with.
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+17665
-17892
lines changed

‎llvm/lib/Target/AArch64/AArch64TargetMachine.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -803,8 +803,9 @@ bool AArch64PassConfig::addILPOpts() {
803803

804804
void AArch64PassConfig::addPreRegAlloc() {
805805
// Change dead register definitions to refer to the zero register.
806-
if (TM->getOptLevel() != CodeGenOptLevel::None &&
807-
EnableDeadRegisterElimination)
806+
// This is beneficial even at -O0 as we can show CMP/CMN in the assembler
807+
// output.
808+
if (EnableDeadRegisterElimination)
808809
addPass(createAArch64DeadRegisterDefinitions());
809810

810811
// Use AdvSIMD scalar instructions whenever profitable.

‎llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-outline_atomics.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
121121
; -O0: eor x8, x0, x8
122122
; -O0: eor x9, x1, x9
123123
; -O0: orr x8, x8, x9
124-
; -O0: subs x8, x8, #0
124+
; -O0: cmp x8, #0
125125
;
126126
; -O1-LABEL: store_atomic_i128_aligned_unordered:
127127
; -O1: ldxp xzr, x8, [x2]
@@ -136,7 +136,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
136136
; -O0: eor x8, x0, x8
137137
; -O0: eor x9, x1, x9
138138
; -O0: orr x8, x8, x9
139-
; -O0: subs x8, x8, #0
139+
; -O0: cmp x8, #0
140140
;
141141
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
142142
; -O1: ldxp xzr, x8, [x2]
@@ -151,7 +151,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
151151
; -O0: eor x8, x0, x8
152152
; -O0: eor x9, x1, x9
153153
; -O0: orr x8, x8, x9
154-
; -O0: subs x8, x8, #0
154+
; -O0: cmp x8, #0
155155
;
156156
; -O1-LABEL: store_atomic_i128_aligned_release:
157157
; -O1: ldxp xzr, x8, [x2]
@@ -166,7 +166,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
166166
; -O0: eor x8, x0, x8
167167
; -O0: eor x9, x1, x9
168168
; -O0: orr x8, x8, x9
169-
; -O0: subs x8, x8, #0
169+
; -O0: cmp x8, #0
170170
;
171171
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
172172
; -O1: ldaxp xzr, x8, [x2]

‎llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
125125
; -O0: eor x8, x10, x8
126126
; -O0: eor x11, x9, x11
127127
; -O0: orr x8, x8, x11
128-
; -O0: subs x8, x8, #0
128+
; -O0: cmp x8, #0
129129
;
130130
; -O1-LABEL: store_atomic_i128_aligned_unordered:
131131
; -O1: ldxp xzr, x8, [x2]
@@ -144,7 +144,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
144144
; -O0: eor x8, x10, x8
145145
; -O0: eor x11, x9, x11
146146
; -O0: orr x8, x8, x11
147-
; -O0: subs x8, x8, #0
147+
; -O0: cmp x8, #0
148148
;
149149
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
150150
; -O1: ldxp xzr, x8, [x2]
@@ -163,7 +163,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
163163
; -O0: eor x8, x10, x8
164164
; -O0: eor x11, x9, x11
165165
; -O0: orr x8, x8, x11
166-
; -O0: subs x8, x8, #0
166+
; -O0: cmp x8, #0
167167
;
168168
; -O1-LABEL: store_atomic_i128_aligned_release:
169169
; -O1: ldxp xzr, x8, [x2]
@@ -182,7 +182,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
182182
; -O0: eor x8, x10, x8
183183
; -O0: eor x11, x9, x11
184184
; -O0: orr x8, x8, x11
185-
; -O0: subs x8, x8, #0
185+
; -O0: cmp x8, #0
186186
;
187187
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
188188
; -O1: ldaxp xzr, x8, [x2]

‎llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-v8_1a.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
121121
; -O0: eor x8, x10, x8
122122
; -O0: eor x11, x9, x11
123123
; -O0: orr x8, x8, x11
124-
; -O0: subs x8, x8, #0
124+
; -O0: cmp x8, #0
125125
;
126126
; -O1-LABEL: store_atomic_i128_aligned_unordered:
127127
; -O1: ldp x4, x5, [x2]
@@ -138,7 +138,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
138138
; -O0: eor x8, x10, x8
139139
; -O0: eor x11, x9, x11
140140
; -O0: orr x8, x8, x11
141-
; -O0: subs x8, x8, #0
141+
; -O0: cmp x8, #0
142142
;
143143
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
144144
; -O1: ldp x4, x5, [x2]
@@ -155,7 +155,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
155155
; -O0: eor x8, x10, x8
156156
; -O0: eor x11, x9, x11
157157
; -O0: orr x8, x8, x11
158-
; -O0: subs x8, x8, #0
158+
; -O0: cmp x8, #0
159159
;
160160
; -O1-LABEL: store_atomic_i128_aligned_release:
161161
; -O1: ldp x4, x5, [x2]
@@ -172,7 +172,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
172172
; -O0: eor x8, x10, x8
173173
; -O0: eor x11, x9, x11
174174
; -O0: orr x8, x8, x11
175-
; -O0: subs x8, x8, #0
175+
; -O0: cmp x8, #0
176176
;
177177
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
178178
; -O1: ldp x4, x5, [x2]

‎llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-v8a.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
125125
; -O0: eor x8, x10, x8
126126
; -O0: eor x11, x9, x11
127127
; -O0: orr x8, x8, x11
128-
; -O0: subs x8, x8, #0
128+
; -O0: cmp x8, #0
129129
;
130130
; -O1-LABEL: store_atomic_i128_aligned_unordered:
131131
; -O1: ldxp xzr, x8, [x2]
@@ -144,7 +144,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
144144
; -O0: eor x8, x10, x8
145145
; -O0: eor x11, x9, x11
146146
; -O0: orr x8, x8, x11
147-
; -O0: subs x8, x8, #0
147+
; -O0: cmp x8, #0
148148
;
149149
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
150150
; -O1: ldxp xzr, x8, [x2]
@@ -163,7 +163,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
163163
; -O0: eor x8, x10, x8
164164
; -O0: eor x11, x9, x11
165165
; -O0: orr x8, x8, x11
166-
; -O0: subs x8, x8, #0
166+
; -O0: cmp x8, #0
167167
;
168168
; -O1-LABEL: store_atomic_i128_aligned_release:
169169
; -O1: ldxp xzr, x8, [x2]
@@ -182,7 +182,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
182182
; -O0: eor x8, x10, x8
183183
; -O0: eor x11, x9, x11
184184
; -O0: orr x8, x8, x11
185-
; -O0: subs x8, x8, #0
185+
; -O0: cmp x8, #0
186186
;
187187
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
188188
; -O1: ldaxp xzr, x8, [x2]

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