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[AArch64] Allow usubo and uaddo to happen for any legal type
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+67
-67
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9 files changed

+67
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -329,9 +329,9 @@ class AArch64TargetLowering : public TargetLowering {
329329

330330
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
331331
bool MathUsed) const override {
332-
// Using overflow ops for overflow checks only should beneficial on
333-
// AArch64.
334-
return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
332+
if (VT.isVector())
333+
return false;
334+
return !isOperationExpand(Opcode, VT);
335335
}
336336

337337
Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,

‎llvm/test/CodeGen/AArch64/abdu-neg.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -355,7 +355,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
355355
; CHECK-LABEL: abd_cmp_i64:
356356
; CHECK: // %bb.0:
357357
; CHECK-NEXT: subs x8, x0, x1
358-
; CHECK-NEXT: cneg x0, x8, hs
358+
; CHECK-NEXT: cneg x0, x8, hi
359359
; CHECK-NEXT: ret
360360
%cmp = icmp ult i64 %a, %b
361361
%ab = sub i64 %a, %b

‎llvm/test/CodeGen/AArch64/arm64-srl-and.ll‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,20 +2,18 @@
22
; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s
33

44
; This used to miscompile:
5-
; The 16-bit -1 should not become 32-bit -1 (sub w8, w8, #1).
65

76
@g = global i16 0, align 4
87
define i32 @srl_and() {
98
; CHECK-LABEL: srl_and:
109
; CHECK: // %bb.0: // %entry
1110
; CHECK-NEXT: adrp x8, :got:g
12-
; CHECK-NEXT: mov w9, #50
1311
; CHECK-NEXT: ldr x8, [x8, :got_lo12:g]
1412
; CHECK-NEXT: ldrh w8, [x8]
15-
; CHECK-NEXT: eor w8, w8, w9
16-
; CHECK-NEXT: mov w9, #65535
17-
; CHECK-NEXT: add w8, w8, w9
18-
; CHECK-NEXT: and w0, w8, w8, lsr #16
13+
; CHECK-NEXT: cmp w8, #50
14+
; CHECK-NEXT: sub w8, w8, #1
15+
; CHECK-NEXT: cset w9, ne
16+
; CHECK-NEXT: and w0, w8, w9
1917
; CHECK-NEXT: ret
2018
entry:
2119
%0 = load i16, ptr @g, align 4

‎llvm/test/CodeGen/AArch64/atomicrmw-uinc-udec-wrap.ll‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -75,10 +75,11 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
7575
; CHECK-NEXT: .LBB4_1: // %atomicrmw.start
7676
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
7777
; CHECK-NEXT: ldaxrb w8, [x0]
78-
; CHECK-NEXT: cmp w8, w1, uxtb
7978
; CHECK-NEXT: sub w9, w8, #1
80-
; CHECK-NEXT: ccmp w8, #0, #4, ls
81-
; CHECK-NEXT: csel w9, w1, w9, eq
79+
; CHECK-NEXT: cmp w8, w1, uxtb
80+
; CHECK-NEXT: and w10, w9, #0xffffff00
81+
; CHECK-NEXT: ccmp w10, #0, #0, ls
82+
; CHECK-NEXT: csel w9, w1, w9, ne
8283
; CHECK-NEXT: stlxrb w10, w9, [x0]
8384
; CHECK-NEXT: cbnz w10, .LBB4_1
8485
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
@@ -94,10 +95,11 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
9495
; CHECK-NEXT: .LBB5_1: // %atomicrmw.start
9596
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
9697
; CHECK-NEXT: ldaxrh w8, [x0]
97-
; CHECK-NEXT: cmp w8, w1, uxth
9898
; CHECK-NEXT: sub w9, w8, #1
99-
; CHECK-NEXT: ccmp w8, #0, #4, ls
100-
; CHECK-NEXT: csel w9, w1, w9, eq
99+
; CHECK-NEXT: cmp w8, w1, uxth
100+
; CHECK-NEXT: and w10, w9, #0xffff0000
101+
; CHECK-NEXT: ccmp w10, #0, #0, ls
102+
; CHECK-NEXT: csel w9, w1, w9, ne
101103
; CHECK-NEXT: stlxrh w10, w9, [x0]
102104
; CHECK-NEXT: cbnz w10, .LBB5_1
103105
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
@@ -113,10 +115,12 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
113115
; CHECK-NEXT: .LBB6_1: // %atomicrmw.start
114116
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
115117
; CHECK-NEXT: ldaxr w8, [x0]
118+
; CHECK-NEXT: subs w9, w8, #1
119+
; CHECK-NEXT: cset w10, lo
116120
; CHECK-NEXT: cmp w8, w1
117-
; CHECK-NEXT: sub w9, w8, #1
118-
; CHECK-NEXT: ccmp w8, #0, #4, ls
119-
; CHECK-NEXT: csel w9, w1, w9, eq
121+
; CHECK-NEXT: csinc w10, w10, wzr, ls
122+
; CHECK-NEXT: cmp w10, #0
123+
; CHECK-NEXT: csel w9, w1, w9, ne
120124
; CHECK-NEXT: stlxr w10, w9, [x0]
121125
; CHECK-NEXT: cbnz w10, .LBB6_1
122126
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
@@ -133,10 +137,12 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
133137
; CHECK-NEXT: .LBB7_1: // %atomicrmw.start
134138
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
135139
; CHECK-NEXT: ldaxr x0, [x8]
140+
; CHECK-NEXT: subs x9, x0, #1
141+
; CHECK-NEXT: cset w10, lo
136142
; CHECK-NEXT: cmp x0, x1
137-
; CHECK-NEXT: sub x9, x0, #1
138-
; CHECK-NEXT: ccmp x0, #0, #4, ls
139-
; CHECK-NEXT: csel x9, x1, x9, eq
143+
; CHECK-NEXT: csinc w10, w10, wzr, ls
144+
; CHECK-NEXT: cmp w10, #0
145+
; CHECK-NEXT: csel x9, x1, x9, ne
140146
; CHECK-NEXT: stlxr w10, x9, [x8]
141147
; CHECK-NEXT: cbnz w10, .LBB7_1
142148
; CHECK-NEXT: // %bb.2: // %atomicrmw.end

‎llvm/test/CodeGen/AArch64/cgp-usubo.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -108,11 +108,9 @@ define i1 @usubo_ugt_constant_op1_i8(i8 %x, ptr %p) nounwind {
108108
define i1 @usubo_eq_constant1_op1_i32(i32 %x, ptr %p) nounwind {
109109
; CHECK-LABEL: usubo_eq_constant1_op1_i32:
110110
; CHECK: // %bb.0:
111-
; CHECK-NEXT: cmp w0, #0
112-
; CHECK-NEXT: sub w9, w0, #1
113-
; CHECK-NEXT: cset w8, eq
114-
; CHECK-NEXT: str w9, [x1]
115-
; CHECK-NEXT: mov w0, w8
111+
; CHECK-NEXT: subs w8, w0, #1
112+
; CHECK-NEXT: cset w0, lo
113+
; CHECK-NEXT: str w8, [x1]
116114
; CHECK-NEXT: ret
117115
%s = add i32 %x, -1
118116
%ov = icmp eq i32 %x, 0

‎llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -192,12 +192,12 @@ define i1 @test_conditional2(i32 %a, i32 %b, ptr %c) {
192192
; CHECK-NEXT: mov w22, #2 ; =0x2
193193
; CHECK-NEXT: LBB3_5: ; %for.cond
194194
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
195-
; CHECK-NEXT: cbz w22, LBB3_8
195+
; CHECK-NEXT: subs w22, w22, #1
196+
; CHECK-NEXT: b.lo LBB3_8
196197
; CHECK-NEXT: ; %bb.6: ; %for.body
197198
; CHECK-NEXT: ; in Loop: Header=BB3_5 Depth=1
198-
; CHECK-NEXT: sub w22, w22, #1
199-
; CHECK-NEXT: orr w9, w21, w20
200199
; CHECK-NEXT: ldr w10, [x19, w22, sxtw #2]
200+
; CHECK-NEXT: orr w9, w21, w20
201201
; CHECK-NEXT: cmp w9, w10
202202
; CHECK-NEXT: b.eq LBB3_5
203203
; CHECK-NEXT: ; %bb.7: ; %if.then
@@ -238,12 +238,12 @@ define i1 @test_conditional2(i32 %a, i32 %b, ptr %c) {
238238
; OUTLINE-ATOMICS-NEXT: cset w8, eq
239239
; OUTLINE-ATOMICS-NEXT: LBB3_1: ; %for.cond
240240
; OUTLINE-ATOMICS-NEXT: ; =>This Inner Loop Header: Depth=1
241-
; OUTLINE-ATOMICS-NEXT: cbz w22, LBB3_4
241+
; OUTLINE-ATOMICS-NEXT: subs w22, w22, #1
242+
; OUTLINE-ATOMICS-NEXT: b.lo LBB3_4
242243
; OUTLINE-ATOMICS-NEXT: ; %bb.2: ; %for.body
243244
; OUTLINE-ATOMICS-NEXT: ; in Loop: Header=BB3_1 Depth=1
244-
; OUTLINE-ATOMICS-NEXT: sub w22, w22, #1
245-
; OUTLINE-ATOMICS-NEXT: orr w9, w21, w20
246245
; OUTLINE-ATOMICS-NEXT: ldr w10, [x19, w22, sxtw #2]
246+
; OUTLINE-ATOMICS-NEXT: orr w9, w21, w20
247247
; OUTLINE-ATOMICS-NEXT: cmp w9, w10
248248
; OUTLINE-ATOMICS-NEXT: b.eq LBB3_1
249249
; OUTLINE-ATOMICS-NEXT: ; %bb.3: ; %if.then

‎llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll‎

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -17,24 +17,22 @@ define dso_local void @f8(i32 noundef %i, i32 noundef %k) #0 {
1717
; CHECK-ASM-NEXT: .cfi_remember_state
1818
; CHECK-ASM-NEXT: // kill: def $w0 killed $w0 def $x0
1919
; CHECK-ASM-NEXT: sxtw x8, w0
20+
; CHECK-ASM-NEXT: mov w9, #10 // =0xa
2021
; CHECK-ASM-NEXT: stp w1, w0, [sp, #8]
21-
; CHECK-ASM-NEXT: cmp x8, #10
22-
; CHECK-ASM-NEXT: b.hi .LBB0_5
22+
; CHECK-ASM-NEXT: subs x9, x9, x8
23+
; CHECK-ASM-NEXT: b.lo .LBB0_5
2324
; CHECK-ASM-NEXT: // %bb.1: // %entry
24-
; CHECK-ASM-NEXT: mov w9, #10 // =0xa
25-
; CHECK-ASM-NEXT: sub x9, x9, x8
2625
; CHECK-ASM-NEXT: cbz x9, .LBB0_5
2726
; CHECK-ASM-NEXT: // %bb.2:
2827
; CHECK-ASM-NEXT: ldrsw x9, [sp, #8]
28+
; CHECK-ASM-NEXT: mov w10, #10 // =0xa
29+
; CHECK-ASM-NEXT: subs x11, x10, x9
2930
; CHECK-ASM-NEXT: adrp x10, .L_MergedGlobals
3031
; CHECK-ASM-NEXT: add x10, x10, :lo12:.L_MergedGlobals
3132
; CHECK-ASM-NEXT: strb wzr, [x10, x8]
32-
; CHECK-ASM-NEXT: cmp x9, #10
33-
; CHECK-ASM-NEXT: b.hi .LBB0_6
33+
; CHECK-ASM-NEXT: b.lo .LBB0_6
3434
; CHECK-ASM-NEXT: // %bb.3:
35-
; CHECK-ASM-NEXT: mov w8, #10 // =0xa
36-
; CHECK-ASM-NEXT: sub x8, x8, x9
37-
; CHECK-ASM-NEXT: cbz x8, .LBB0_6
35+
; CHECK-ASM-NEXT: cbz x11, .LBB0_6
3836
; CHECK-ASM-NEXT: // %bb.4:
3937
; CHECK-ASM-NEXT: add x8, x10, x9
4038
; CHECK-ASM-NEXT: strb wzr, [x8, #10]

‎llvm/test/CodeGen/AArch64/sat-add.ll‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,9 @@ define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
2525
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
2626
; CHECK: // %bb.0:
2727
; CHECK-NEXT: and w8, w0, #0xff
28-
; CHECK-NEXT: add w8, w8, #42
29-
; CHECK-NEXT: tst w8, #0x100
30-
; CHECK-NEXT: csinv w0, w8, wzr, eq
28+
; CHECK-NEXT: add w9, w0, #42
29+
; CHECK-NEXT: cmp w8, w9, uxtb
30+
; CHECK-NEXT: csinv w0, w9, wzr, ls
3131
; CHECK-NEXT: ret
3232
%a = add i8 %x, 42
3333
%c = icmp ugt i8 %x, %a
@@ -68,9 +68,9 @@ define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
6868
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
6969
; CHECK: // %bb.0:
7070
; CHECK-NEXT: and w8, w0, #0xffff
71-
; CHECK-NEXT: add w8, w8, #42
72-
; CHECK-NEXT: tst w8, #0x10000
73-
; CHECK-NEXT: csinv w0, w8, wzr, eq
71+
; CHECK-NEXT: add w9, w0, #42
72+
; CHECK-NEXT: cmp w8, w9, uxth
73+
; CHECK-NEXT: csinv w0, w9, wzr, ls
7474
; CHECK-NEXT: ret
7575
%a = add i16 %x, 42
7676
%c = icmp ugt i16 %x, %a
@@ -188,9 +188,9 @@ define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
188188
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
189189
; CHECK: // %bb.0:
190190
; CHECK-NEXT: and w8, w0, #0xff
191-
; CHECK-NEXT: add w8, w8, w1, uxtb
192-
; CHECK-NEXT: tst w8, #0x100
193-
; CHECK-NEXT: csinv w0, w8, wzr, eq
191+
; CHECK-NEXT: add w9, w0, w1
192+
; CHECK-NEXT: cmp w8, w9, uxtb
193+
; CHECK-NEXT: csinv w0, w9, wzr, ls
194194
; CHECK-NEXT: ret
195195
%a = add i8 %x, %y
196196
%c = icmp ugt i8 %x, %a
@@ -201,11 +201,11 @@ define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
201201
define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
202202
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
203203
; CHECK: // %bb.0:
204-
; CHECK-NEXT: and w8, w1, #0xff
205-
; CHECK-NEXT: add w9, w0, w1
206-
; CHECK-NEXT: add w8, w8, w0, uxtb
207-
; CHECK-NEXT: tst w8, #0x100
208-
; CHECK-NEXT: csinv w0, w9, wzr, eq
204+
; CHECK-NEXT: and w8, w0, #0xff
205+
; CHECK-NEXT: mvn w9, w1
206+
; CHECK-NEXT: add w10, w0, w1
207+
; CHECK-NEXT: cmp w8, w9, uxtb
208+
; CHECK-NEXT: csinv w0, w10, wzr, ls
209209
; CHECK-NEXT: ret
210210
%noty = xor i8 %y, -1
211211
%a = add i8 %x, %y
@@ -234,9 +234,9 @@ define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
234234
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
235235
; CHECK: // %bb.0:
236236
; CHECK-NEXT: and w8, w0, #0xffff
237-
; CHECK-NEXT: add w8, w8, w1, uxth
238-
; CHECK-NEXT: tst w8, #0x10000
239-
; CHECK-NEXT: csinv w0, w8, wzr, eq
237+
; CHECK-NEXT: add w9, w0, w1
238+
; CHECK-NEXT: cmp w8, w9, uxth
239+
; CHECK-NEXT: csinv w0, w9, wzr, ls
240240
; CHECK-NEXT: ret
241241
%a = add i16 %x, %y
242242
%c = icmp ugt i16 %x, %a
@@ -247,11 +247,11 @@ define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
247247
define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
248248
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
249249
; CHECK: // %bb.0:
250-
; CHECK-NEXT: and w8, w1, #0xffff
251-
; CHECK-NEXT: add w9, w0, w1
252-
; CHECK-NEXT: add w8, w8, w0, uxth
253-
; CHECK-NEXT: tst w8, #0x10000
254-
; CHECK-NEXT: csinv w0, w9, wzr, eq
250+
; CHECK-NEXT: and w8, w0, #0xffff
251+
; CHECK-NEXT: mvn w9, w1
252+
; CHECK-NEXT: add w10, w0, w1
253+
; CHECK-NEXT: cmp w8, w9, uxth
254+
; CHECK-NEXT: csinv w0, w10, wzr, ls
255255
; CHECK-NEXT: ret
256256
%noty = xor i16 %y, -1
257257
%a = add i16 %x, %y

‎llvm/test/CodeGen/AArch64/signed-truncation-check.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -313,9 +313,9 @@ define i1 @add_ultcmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
313313
define i1 @add_ultcmp_bad_i8_i16(i16 %x) nounwind {
314314
; CHECK-LABEL: add_ultcmp_bad_i8_i16:
315315
; CHECK: // %bb.0:
316-
; CHECK-NEXT: and w8, w0, #0xffff
317-
; CHECK-NEXT: add w8, w8, #128
318-
; CHECK-NEXT: lsr w0, w8, #16
316+
; CHECK-NEXT: add w8, w0, #128
317+
; CHECK-NEXT: tst w8, #0xff80
318+
; CHECK-NEXT: cset w0, eq
319319
; CHECK-NEXT: ret
320320
%tmp0 = add i16 %x, 128 ; 1U << (8-1)
321321
%tmp1 = icmp ult i16 %tmp0, 128 ; 1U << (8-1)

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