DS -> SX in MxLists aliases

S and UX/OX are the common parts of SchedWrite names for strided and segmented
operations, hence "SX" suffix, followed by EEW.

Author: ppenzin

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

@@ -562,7 +562,7 @@ multiclass SiFive7WriteResBase<int VLEN,
   // resource, we do not need to use LMULSEWXXX constructors. However, we do
   // use the SEW from the name to determine the number of Cycles.
 
-  foreach mx = SchedMxListDS8 in {
+  foreach mx = SchedMxListSX8 in {
     defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -583,7 +583,7 @@ multiclass SiFive7WriteResBase<int VLEN,
     }
   }
 
-  foreach mx = SchedMxListDS16 in {
+  foreach mx = SchedMxListSX16 in {
     defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -603,7 +603,7 @@ multiclass SiFive7WriteResBase<int VLEN,
       defm : LMULWriteResMX<"WriteVSTOX16", [VCQ, VS], mx, IsWorstCase>;
     }
   }
-  foreach mx = SchedMxListDS32 in {
+  foreach mx = SchedMxListSX32 in {
     defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -623,7 +623,7 @@ multiclass SiFive7WriteResBase<int VLEN,
       defm : LMULWriteResMX<"WriteVSTOX32", [VCQ, VS], mx, IsWorstCase>;
     }
   }
-  foreach mx = SchedMxListDS64 in {
+  foreach mx = SchedMxListSX64 in {
     defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;

llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td

@@ -437,7 +437,7 @@ foreach mx = SchedMxList in {
   defm "" : LMULWriteResMX<"WriteVSTM",    [AscalonLS], mx, IsWorstCase>;
 }
 
-foreach mx = SchedMxListDS8 in {
+foreach mx = SchedMxListSX8 in {
   defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
   defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
   let Latency = Cycles in {
@@ -449,7 +449,7 @@ foreach mx = SchedMxListDS8 in {
     defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
   }
 }
-foreach mx = SchedMxListDS16 in {
+foreach mx = SchedMxListSX16 in {
   defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
   defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
   let Latency = Cycles in {
@@ -461,7 +461,7 @@ foreach mx = SchedMxListDS16 in {
     defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
   }
 }
-foreach mx = SchedMxListDS32 in {
+foreach mx = SchedMxListSX32 in {
   defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
   defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
   let Latency = Cycles in {
@@ -473,7 +473,7 @@ foreach mx = SchedMxListDS32 in {
     defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
   }
 }
-foreach mx = SchedMxListDS64 in {
+foreach mx = SchedMxListSX64 in {
   defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
   defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
   let Latency = Cycles in {

llvm/lib/Target/RISCV/RISCVScheduleV.td

@@ -20,13 +20,13 @@ defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = SchedMxListF;
 // Used for indexed and strided loads of 8 bit lanes, same as full MX list
-defvar SchedMxListDS8 = SchedMxList;
+defvar SchedMxListSX8 = SchedMxList;
 // Used for indexed and strided loads of 16 bit lanes
-defvar SchedMxListDS16 = SchedMxListF;
+defvar SchedMxListSX16 = SchedMxListF;
 // Used for indexed and strided loads of 32 bit lanes
-defvar SchedMxListDS32 = !listremove(SchedMxListDS16, ["MF4"]);
+defvar SchedMxListSX32 = !listremove(SchedMxListSX16, ["MF4"]);
 // Used for indexed and strided loads of 64 bit lanes
-defvar SchedMxListDS64 = !listremove(SchedMxListDS32, ["MF2"]);
+defvar SchedMxListSX64 = !listremove(SchedMxListSX32, ["MF2"]);
 
 class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
   assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";