Skip to content

Commit eeba6f4

Browse files
zhaoqi5zhaoqi5
authored
[LoongArch] Add generation support for [x]{vandn/vorn}.v (#158526)
1 parent cedceeb commit eeba6f4

File tree

8 files changed

+50
-66
lines changed

8 files changed

+50
-66
lines changed

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1389,6 +1389,14 @@ def : Pat<(xor (vt LASX256:$xj), (vt LASX256:$xk)),
13891389
foreach vt = [v32i8, v16i16, v8i32, v4i64] in
13901390
def : Pat<(vnot (or (vt LASX256:$xj), (vt LASX256:$xk))),
13911391
(XVNOR_V LASX256:$xj, LASX256:$xk)>;
1392+
// XVANDN_V
1393+
foreach vt = [v32i8, v16i16, v8i32, v4i64] in
1394+
def : Pat<(and (vt (vnot LASX256:$xj)), (vt LASX256:$xk)),
1395+
(XVANDN_V LASX256:$xj, LASX256:$xk)>;
1396+
// XVORN_V
1397+
foreach vt = [v32i8, v16i16, v8i32, v4i64] in
1398+
def : Pat<(or (vt LASX256:$xj), (vt (vnot LASX256:$xk))),
1399+
(XVORN_V LASX256:$xj, LASX256:$xk)>;
13921400

13931401
// XVANDI_B
13941402
def : Pat<(and (v32i8 LASX256:$xj), (v32i8 (SplatPat_uimm8 uimm8:$imm))),

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1583,6 +1583,14 @@ def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)),
15831583
foreach vt = [v16i8, v8i16, v4i32, v2i64] in
15841584
def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))),
15851585
(VNOR_V LSX128:$vj, LSX128:$vk)>;
1586+
// VANDN_V
1587+
foreach vt = [v16i8, v8i16, v4i32, v2i64] in
1588+
def : Pat<(and (vt (vnot LSX128:$vj)), (vt LSX128:$vk)),
1589+
(VANDN_V LSX128:$vj, LSX128:$vk)>;
1590+
// VORN_V
1591+
foreach vt = [v16i8, v8i16, v4i32, v2i64] in
1592+
def : Pat<(or (vt LSX128:$vj), (vt (vnot LSX128:$vk))),
1593+
(VORN_V LSX128:$vj, LSX128:$vk)>;
15861594

15871595
// VANDI_B
15881596
def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))),

‎llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,7 @@ define <4 x i64> @lasx_xvbitclr_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
4747
; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
4848
; LA32-NEXT: xvrepli.d $xr2, 1
4949
; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1
50-
; LA32-NEXT: xvrepli.b $xr2, -1
51-
; LA32-NEXT: xvxor.v $xr1, $xr1, $xr2
52-
; LA32-NEXT: xvand.v $xr0, $xr0, $xr1
50+
; LA32-NEXT: xvandn.v $xr0, $xr1, $xr0
5351
; LA32-NEXT: ret
5452
;
5553
; LA64-LABEL: lasx_xvbitclr_d:

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll‎

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ define void @andn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
77
; CHECK: # %bb.0: # %entry
88
; CHECK-NEXT: xvld $xr0, $a1, 0
99
; CHECK-NEXT: xvld $xr1, $a2, 0
10-
; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
11-
; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
10+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
1211
; CHECK-NEXT: xvst $xr0, $a0, 0
1312
; CHECK-NEXT: ret
1413
entry:
@@ -25,9 +24,7 @@ define void @andn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
2524
; CHECK: # %bb.0: # %entry
2625
; CHECK-NEXT: xvld $xr0, $a1, 0
2726
; CHECK-NEXT: xvld $xr1, $a2, 0
28-
; CHECK-NEXT: xvrepli.b $xr2, -1
29-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
30-
; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
27+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
3128
; CHECK-NEXT: xvst $xr0, $a0, 0
3229
; CHECK-NEXT: ret
3330
entry:
@@ -44,9 +41,7 @@ define void @andn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
4441
; CHECK: # %bb.0: # %entry
4542
; CHECK-NEXT: xvld $xr0, $a1, 0
4643
; CHECK-NEXT: xvld $xr1, $a2, 0
47-
; CHECK-NEXT: xvrepli.b $xr2, -1
48-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
49-
; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
44+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
5045
; CHECK-NEXT: xvst $xr0, $a0, 0
5146
; CHECK-NEXT: ret
5247
entry:
@@ -63,9 +58,7 @@ define void @andn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
6358
; CHECK: # %bb.0: # %entry
6459
; CHECK-NEXT: xvld $xr0, $a1, 0
6560
; CHECK-NEXT: xvld $xr1, $a2, 0
66-
; CHECK-NEXT: xvrepli.b $xr2, -1
67-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
68-
; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
61+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
6962
; CHECK-NEXT: xvst $xr0, $a0, 0
7063
; CHECK-NEXT: ret
7164
entry:

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll‎

Lines changed: 12 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,9 @@
55
define void @orn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
66
; CHECK-LABEL: orn_v32i8:
77
; CHECK: # %bb.0: # %entry
8-
; CHECK-NEXT: xvld $xr0, $a2, 0
9-
; CHECK-NEXT: xvld $xr1, $a1, 0
10-
; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
11-
; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
8+
; CHECK-NEXT: xvld $xr0, $a1, 0
9+
; CHECK-NEXT: xvld $xr1, $a2, 0
10+
; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
1211
; CHECK-NEXT: xvst $xr0, $a0, 0
1312
; CHECK-NEXT: ret
1413
entry:
@@ -23,11 +22,9 @@ entry:
2322
define void @orn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
2423
; CHECK-LABEL: orn_v16i16:
2524
; CHECK: # %bb.0: # %entry
26-
; CHECK-NEXT: xvld $xr0, $a2, 0
27-
; CHECK-NEXT: xvld $xr1, $a1, 0
28-
; CHECK-NEXT: xvrepli.b $xr2, -1
29-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
30-
; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
25+
; CHECK-NEXT: xvld $xr0, $a1, 0
26+
; CHECK-NEXT: xvld $xr1, $a2, 0
27+
; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
3128
; CHECK-NEXT: xvst $xr0, $a0, 0
3229
; CHECK-NEXT: ret
3330
entry:
@@ -42,11 +39,9 @@ entry:
4239
define void @orn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
4340
; CHECK-LABEL: orn_v8i32:
4441
; CHECK: # %bb.0: # %entry
45-
; CHECK-NEXT: xvld $xr0, $a2, 0
46-
; CHECK-NEXT: xvld $xr1, $a1, 0
47-
; CHECK-NEXT: xvrepli.b $xr2, -1
48-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
49-
; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
42+
; CHECK-NEXT: xvld $xr0, $a1, 0
43+
; CHECK-NEXT: xvld $xr1, $a2, 0
44+
; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
5045
; CHECK-NEXT: xvst $xr0, $a0, 0
5146
; CHECK-NEXT: ret
5247
entry:
@@ -61,11 +56,9 @@ entry:
6156
define void @orn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
6257
; CHECK-LABEL: orn_v4i64:
6358
; CHECK: # %bb.0: # %entry
64-
; CHECK-NEXT: xvld $xr0, $a2, 0
65-
; CHECK-NEXT: xvld $xr1, $a1, 0
66-
; CHECK-NEXT: xvrepli.b $xr2, -1
67-
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
68-
; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
59+
; CHECK-NEXT: xvld $xr0, $a1, 0
60+
; CHECK-NEXT: xvld $xr1, $a2, 0
61+
; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
6962
; CHECK-NEXT: xvst $xr0, $a0, 0
7063
; CHECK-NEXT: ret
7164
entry:

‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,7 @@ define <2 x i64> @lsx_vbitclr_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
4747
; LA32-NEXT: vand.v $vr1, $vr1, $vr2
4848
; LA32-NEXT: vrepli.d $vr2, 1
4949
; LA32-NEXT: vsll.d $vr1, $vr2, $vr1
50-
; LA32-NEXT: vrepli.b $vr2, -1
51-
; LA32-NEXT: vxor.v $vr1, $vr1, $vr2
52-
; LA32-NEXT: vand.v $vr0, $vr0, $vr1
50+
; LA32-NEXT: vandn.v $vr0, $vr1, $vr0
5351
; LA32-NEXT: ret
5452
;
5553
; LA64-LABEL: lsx_vbitclr_d:

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll‎

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ define void @andn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
77
; CHECK: # %bb.0: # %entry
88
; CHECK-NEXT: vld $vr0, $a1, 0
99
; CHECK-NEXT: vld $vr1, $a2, 0
10-
; CHECK-NEXT: vxori.b $vr0, $vr0, 255
11-
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
10+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
1211
; CHECK-NEXT: vst $vr0, $a0, 0
1312
; CHECK-NEXT: ret
1413
entry:
@@ -25,9 +24,7 @@ define void @andn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
2524
; CHECK: # %bb.0: # %entry
2625
; CHECK-NEXT: vld $vr0, $a1, 0
2726
; CHECK-NEXT: vld $vr1, $a2, 0
28-
; CHECK-NEXT: vrepli.b $vr2, -1
29-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
30-
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
27+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
3128
; CHECK-NEXT: vst $vr0, $a0, 0
3229
; CHECK-NEXT: ret
3330
entry:
@@ -44,9 +41,7 @@ define void @andn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
4441
; CHECK: # %bb.0: # %entry
4542
; CHECK-NEXT: vld $vr0, $a1, 0
4643
; CHECK-NEXT: vld $vr1, $a2, 0
47-
; CHECK-NEXT: vrepli.b $vr2, -1
48-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
49-
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
44+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
5045
; CHECK-NEXT: vst $vr0, $a0, 0
5146
; CHECK-NEXT: ret
5247
entry:
@@ -63,9 +58,7 @@ define void @andn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
6358
; CHECK: # %bb.0: # %entry
6459
; CHECK-NEXT: vld $vr0, $a1, 0
6560
; CHECK-NEXT: vld $vr1, $a2, 0
66-
; CHECK-NEXT: vrepli.b $vr2, -1
67-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
68-
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
61+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
6962
; CHECK-NEXT: vst $vr0, $a0, 0
7063
; CHECK-NEXT: ret
7164
entry:

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll‎

Lines changed: 12 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,9 @@
55
define void @orn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
66
; CHECK-LABEL: orn_v16i8:
77
; CHECK: # %bb.0: # %entry
8-
; CHECK-NEXT: vld $vr0, $a2, 0
9-
; CHECK-NEXT: vld $vr1, $a1, 0
10-
; CHECK-NEXT: vxori.b $vr0, $vr0, 255
11-
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
8+
; CHECK-NEXT: vld $vr0, $a1, 0
9+
; CHECK-NEXT: vld $vr1, $a2, 0
10+
; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
1211
; CHECK-NEXT: vst $vr0, $a0, 0
1312
; CHECK-NEXT: ret
1413
entry:
@@ -23,11 +22,9 @@ entry:
2322
define void @orn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
2423
; CHECK-LABEL: orn_v8i16:
2524
; CHECK: # %bb.0: # %entry
26-
; CHECK-NEXT: vld $vr0, $a2, 0
27-
; CHECK-NEXT: vld $vr1, $a1, 0
28-
; CHECK-NEXT: vrepli.b $vr2, -1
29-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
30-
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
25+
; CHECK-NEXT: vld $vr0, $a1, 0
26+
; CHECK-NEXT: vld $vr1, $a2, 0
27+
; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
3128
; CHECK-NEXT: vst $vr0, $a0, 0
3229
; CHECK-NEXT: ret
3330
entry:
@@ -42,11 +39,9 @@ entry:
4239
define void @orn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
4340
; CHECK-LABEL: orn_v4i32:
4441
; CHECK: # %bb.0: # %entry
45-
; CHECK-NEXT: vld $vr0, $a2, 0
46-
; CHECK-NEXT: vld $vr1, $a1, 0
47-
; CHECK-NEXT: vrepli.b $vr2, -1
48-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
49-
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
42+
; CHECK-NEXT: vld $vr0, $a1, 0
43+
; CHECK-NEXT: vld $vr1, $a2, 0
44+
; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
5045
; CHECK-NEXT: vst $vr0, $a0, 0
5146
; CHECK-NEXT: ret
5247
entry:
@@ -61,11 +56,9 @@ entry:
6156
define void @orn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
6257
; CHECK-LABEL: orn_v2i64:
6358
; CHECK: # %bb.0: # %entry
64-
; CHECK-NEXT: vld $vr0, $a2, 0
65-
; CHECK-NEXT: vld $vr1, $a1, 0
66-
; CHECK-NEXT: vrepli.b $vr2, -1
67-
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
68-
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
59+
; CHECK-NEXT: vld $vr0, $a1, 0
60+
; CHECK-NEXT: vld $vr1, $a2, 0
61+
; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
6962
; CHECK-NEXT: vst $vr0, $a0, 0
7063
; CHECK-NEXT: ret
7164
entry:

0 commit comments

Comments
 (0)