Move into AArch64ISD::FCVTZ[S|U]_HALF

Author: mrkajetanp

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -424,6 +424,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
   void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
   void SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale,
                              unsigned Opc_rr, unsigned Opc_ri);
+  void SelectFCVT_FPTOINT_Half(SDNode *N, unsigned Opc);
   std::tuple<unsigned, SDValue, SDValue>
   findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr, unsigned Opc_ri,
                            const SDValue &OldBase, const SDValue &OldOffset,
@@ -2536,6 +2537,25 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
   ReplaceNode(N, St);
 }
 
+// Select f16 -> i16 conversions
+// Since i16 is an illegal type, they need to return an i32 result
+void AArch64DAGToDAGISel::SelectFCVT_FPTOINT_Half(SDNode *N, unsigned int Opc) {
+  SDLoc DL(N);
+  SDValue SrcVal = N->getOperand(0);
+  SDNode *Cvt = CurDAG->getMachineNode(Opc, DL, MVT::f16, SrcVal);
+  SDValue Sign = CurDAG->getTargetConstant(-1, DL, MVT::i64);
+  SDValue Hsub = CurDAG->getTargetConstant(AArch64::hsub, DL, MVT::i32);
+  SDNode *SubregToReg = CurDAG->getMachineNode(
+      TargetOpcode::SUBREG_TO_REG, DL, MVT::v8f16, Sign, SDValue(Cvt, 0), Hsub);
+  SDValue Ssub = CurDAG->getTargetConstant(AArch64::ssub, DL, MVT::i32);
+  SDNode *Extract =
+      CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f32,
+                             SDValue(SubregToReg, 0), Ssub);
+  SDNode *Result = CurDAG->getMachineNode(AArch64::FMOVSWr, DL, MVT::i32,
+                                          SDValue(Extract, 0));
+  ReplaceNode(N, Result);
+}
+
 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
                                        unsigned &Opc, SDValue &Opd0,
                                        unsigned &LSB, unsigned &MSB,
@@ -7359,6 +7379,14 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
     }
     break;
   }
+  case AArch64ISD::FCVTZS_HALF: {
+    SelectFCVT_FPTOINT_Half(Node, AArch64::FCVTZSv1f16);
+    return;
+  }
+  case AArch64ISD::FCVTZU_HALF: {
+    SelectFCVT_FPTOINT_Half(Node, AArch64::FCVTZUv1f16);
+    return;
+  }
   }
 
   // Select the default instruction

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -4912,21 +4912,9 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
     return SDValue();
 
   if (SrcVT == MVT::f16 && SatVT == MVT::i16 && DstVT == MVT::i32) {
-    auto Opcode = (Op.getOpcode() == ISD::FP_TO_SINT_SAT)
-                      ? AArch64::FCVTZSv1f16
-                      : AArch64::FCVTZUv1f16;
-    auto Cvt = SDValue(DAG.getMachineNode(Opcode, DL, MVT::f16, SrcVal), 0);
-    auto Sign = DAG.getTargetConstant(-1, DL, MVT::i64);
-    auto Hsub = DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32);
-    auto SubregToReg =
-        SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, DL, MVT::v8f16,
-                                   Sign, Cvt, Hsub),
-                0);
-    auto Ssub = DAG.getTargetConstant(AArch64::ssub, DL, MVT::i32);
-    auto Extract = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
-                                              MVT::f32, SubregToReg, Ssub),
-                           0);
-    return DAG.getBitcast(MVT::i32, Extract);
+    if (Op.getOpcode() == ISD::FP_TO_SINT_SAT)
+      return DAG.getNode(AArch64ISD::FCVTZS_HALF, DL, DstVT, SrcVal);
+    return DAG.getNode(AArch64ISD::FCVTZU_HALF, DL, DstVT, SrcVal);
   }
 
   SDValue NativeCvt =

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -989,6 +989,9 @@ def AArch64fcvtxnv: PatFrags<(ops node:$Rn),
                                  [(int_aarch64_neon_fcvtxn node:$Rn),
                                   (AArch64fcvtxn_n node:$Rn)]>;
 
+def AArch64fcvtzs_half : SDNode<"AArch64ISD::FCVTZS_HALF", SDTFPToIntOp>;
+def AArch64fcvtzu_half : SDNode<"AArch64ISD::FCVTZU_HALF", SDTFPToIntOp>;
+
 //def Aarch64softf32tobf16v8: SDNode<"AArch64ISD::", SDTFPRoundOp>;
 
 // Vector immediate ops