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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 |
| 2 | +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -stop-after=irtranslator -o - %s | FileCheck %s |
| 3 | + |
| 4 | +define i32 @reloc_constant() { |
| 5 | + ; CHECK-LABEL: name: reloc_constant |
| 6 | + ; CHECK: bb.1 (%ir-block.0): |
| 7 | + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.reloc.constant), !0 |
| 8 | + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.reloc.constant), <0x{{[0-9a-f]+}}> |
| 9 | + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[INT]], [[INT1]] |
| 10 | + ; CHECK-NEXT: $vgpr0 = COPY [[ADD]](s32) |
| 11 | + ; CHECK-NEXT: SI_RETURN implicit $vgpr0 |
| 12 | + %val0 = call i32 @llvm.amdgcn.reloc.constant(metadata !0) |
| 13 | + %val1 = call i32 @llvm.amdgcn.reloc.constant(metadata i32 4) |
| 14 | + %res = add i32 %val0, %val1 |
| 15 | + ret i32 %res |
| 16 | +} |
| 17 | + |
| 18 | +define i32 @reloc_other_constant() { |
| 19 | + ; CHECK-LABEL: name: reloc_other_constant |
| 20 | + ; CHECK: bb.1 (%ir-block.0): |
| 21 | + ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.reloc.constant), !0 |
| 22 | + ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.reloc.constant), <0x{{[0-9a-f]+}}> |
| 23 | + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[INT]], [[INT1]] |
| 24 | + ; CHECK-NEXT: $vgpr0 = COPY [[ADD]](s32) |
| 25 | + ; CHECK-NEXT: SI_RETURN implicit $vgpr0 |
| 26 | + %val0 = call i32 @llvm.amdgcn.reloc.constant(metadata !0) |
| 27 | + %val1 = call i32 @llvm.amdgcn.reloc.constant(metadata i32 8) |
| 28 | + %res = add i32 %val0, %val1 |
| 29 | + ret i32 %res |
| 30 | +} |
| 31 | + |
| 32 | +declare i32 @llvm.amdgcn.reloc.constant(metadata) #0 |
| 33 | + |
| 34 | +attributes #0 = { nounwind readnone speculatable willreturn } |
| 35 | + |
| 36 | +!0 = !{!"arst"} |
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