Renamed pass

Signed-off-by: Mikhail R. Gadelha <[email protected]>

Author: mikhailramalho

llvm/lib/Target/RISCV/RISCV.h

@@ -40,8 +40,8 @@ void initializeRISCVLandingPadSetupPass(PassRegistry &);
 FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
                                  CodeGenOptLevel OptLevel);
 
-FunctionPass *createRISCVLateOptPass();
-void initializeRISCVLateOptPass(PassRegistry &);
+FunctionPass *createRISCVLateBranchOptPass();
+void initializeRISCVLateBranchOptPass(PassRegistry &);
 
 FunctionPass *createRISCVMakeCompressibleOptPass();
 void initializeRISCVMakeCompressibleOptPass(PassRegistry &);

llvm/lib/Target/RISCV/RISCVLateOpt.cpp

@@ -1,4 +1,4 @@
-//===-- RISCVLateOpt.cpp - Late stage optimization ------------------------===//
+//===-- RISCVLateBranchOpt.cpp - Late stage optimization ------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -17,17 +17,16 @@
 
 using namespace llvm;
 
-#define DEBUG_TYPE "riscv-late-opt"
-#define RISCV_LATE_OPT_NAME "RISC-V Late Stage Optimizations"
+#define RISCV_LATE_BRANCH_OPT_NAME "RISC-V Late Branch Optimisation Pass"
 
 namespace {
 
-struct RISCVLateOpt : public MachineFunctionPass {
+struct RISCVLateBranchOpt : public MachineFunctionPass {
   static char ID;
 
-  RISCVLateOpt() : MachineFunctionPass(ID) {}
+  RISCVLateBranchOpt() : MachineFunctionPass(ID) {}
 
-  StringRef getPassName() const override { return RISCV_LATE_OPT_NAME; }
+  StringRef getPassName() const override { return RISCV_LATE_BRANCH_OPT_NAME; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
@@ -42,11 +41,11 @@ struct RISCVLateOpt : public MachineFunctionPass {
 };
 } // namespace
 
-char RISCVLateOpt::ID = 0;
-INITIALIZE_PASS(RISCVLateOpt, "riscv-late-opt", RISCV_LATE_OPT_NAME, false,
-                false)
+char RISCVLateBranchOpt::ID = 0;
+INITIALIZE_PASS(RISCVLateBranchOpt, "riscv-late-branch-opt",
+                RISCV_LATE_BRANCH_OPT_NAME, false, false)
 
-bool RISCVLateOpt::runOnBasicBlock(MachineBasicBlock &MBB) const {
+bool RISCVLateBranchOpt::runOnBasicBlock(MachineBasicBlock &MBB) const {
   MachineBasicBlock *TBB, *FBB;
   SmallVector<MachineOperand, 4> Cond;
   if (RII->analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false))
@@ -94,7 +93,7 @@ bool RISCVLateOpt::runOnBasicBlock(MachineBasicBlock &MBB) const {
   return true;
 }
 
-bool RISCVLateOpt::runOnMachineFunction(MachineFunction &Fn) {
+bool RISCVLateBranchOpt::runOnMachineFunction(MachineFunction &Fn) {
   if (skipFunction(Fn.getFunction()))
     return false;
 
@@ -107,4 +106,4 @@ bool RISCVLateOpt::runOnMachineFunction(MachineFunction &Fn) {
   return Changed;
 }
 
-FunctionPass *llvm::createRISCVLateOptPass() { return new RISCVLateOpt(); }
+FunctionPass *llvm::createRISCVLateBranchOptPass() { return new RISCVLateBranchOpt(); }

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

@@ -127,7 +127,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   initializeRISCVPostLegalizerCombinerPass(*PR);
   initializeKCFIPass(*PR);
   initializeRISCVDeadRegisterDefinitionsPass(*PR);
-  initializeRISCVLateOptPass(*PR);
+  initializeRISCVLateBranchOptPass(*PR);
   initializeRISCVMakeCompressibleOptPass(*PR);
   initializeRISCVGatherScatterLoweringPass(*PR);
   initializeRISCVCodeGenPreparePass(*PR);
@@ -567,7 +567,7 @@ void RISCVPassConfig::addPreEmitPass() {
       EnableRISCVCopyPropagation)
     addPass(createMachineCopyPropagationPass(true));
   if (TM->getOptLevel() >= CodeGenOptLevel::Default)
-    addPass(createRISCVLateOptPass());
+    addPass(createRISCVLateBranchOptPass());
   addPass(&BranchRelaxationPassID);
   addPass(createRISCVMakeCompressibleOptPass());
 }

llvm/test/CodeGen/RISCV/O3-pipeline.ll

@@ -194,7 +194,7 @@
 ; CHECK-NEXT:       Insert XRay ops
 ; CHECK-NEXT:       Implement the 'patchable-function' attribute
 ; CHECK-NEXT:       Machine Copy Propagation Pass
-; CHECK-NEXT:       RISC-V Late Stage Optimizations
+; CHECK-NEXT:       RISC-V Late Branch Optimisation Pass
 ; CHECK-NEXT:       Branch relaxation pass
 ; CHECK-NEXT:       RISC-V Make Compressible
 ; CHECK-NEXT:       Contiguously Lay Out Funclets