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1 parent 16c84c4 commit efce8f1Copy full SHA for efce8f1
llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -41117,8 +41117,7 @@ static SDValue combineX86ShufflesRecursively(
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// Peek through vector widenings and set out of bounds mask indices to undef.
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// TODO: Can resolveTargetShuffleInputsAndMask do some of this?
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- for (unsigned I = 0, E = Ops.size(); I != E; ++I) {
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- SDValue &Op = Ops[I];
+ for (auto [I, Op] : enumerate(Ops)) {
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if (Op.getOpcode() == ISD::INSERT_SUBVECTOR && Op.getOperand(0).isUndef() &&
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isNullConstant(Op.getOperand(2))) {
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Op = Op.getOperand(1);
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