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[InstCombine] Fold `ceil(X >> C) == 0 -> X == 0` update test 1 address review comments rm header 1 1
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‎llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp‎

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@@ -1298,6 +1298,7 @@ Instruction *InstCombinerImpl::foldICmpWithZero(ICmpInst &Cmp) {
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// eq/ne (mul X, Y)) with (icmp eq/ne X/Y) and if X/Y is known non-zero that
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// will fold to a constant elsewhere.
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}
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return nullptr;
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}
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‎llvm/test/Transforms/InstCombine/ceil-shift.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i1 @ceil_shift4(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%quot = lshr i32 %arg0, 4
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%rem = and i32 %arg0, 15
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%is_zero = icmp eq i32 %quot_or_rem, 0
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ret i1 %is_zero
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}
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define i1 @ceil_shift4_add(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4_add(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%quot = lshr i32 %arg0, 4
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%rem = and i32 %arg0, 15
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%ceil = add i32 %quot, %zext_has_rem
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%res = icmp eq i32 %ceil, 0
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ret i1 %res
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}
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define i1 @ceil_shift6(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift6(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 6
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 63
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%quot = lshr i32 %arg0, 6
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%rem = and i32 %arg0, 63
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift6_ne(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift6_ne(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 6
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 63
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%quot = lshr i32 %arg0, 6
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%rem = and i32 %arg0, 63
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp ne i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift11(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift11(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 11
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 2047
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%quot = lshr i32 %arg0, 11
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%rem = and i32 %arg0, 2047
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift11_ne(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift11_ne(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 6
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 63
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%quot = lshr i32 %arg0, 6
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%rem = and i32 %arg0, 63
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp ne i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift0(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift0(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%quot = lshr i32 %arg0, 0
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%rem = and i32 %arg0, 0
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift4_comm(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4_comm(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%quot = lshr i32 %arg0, 4
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%rem = and i32 %arg0, 15
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %zext_has_rem, %quot
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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declare void @use(i32)
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define i1 @ceil_shift4_used_1(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4_used_1(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: call void @use(i32 [[TMP1]])
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[TMP1]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%quot = lshr i32 %arg0, 4
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call void @use(i32 %quot)
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%rem = and i32 %arg0, 15
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift4_used_5(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4_used_5(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: call void @use(i32 [[TMP5]])
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%quot = lshr i32 %arg0, 4
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%rem = and i32 %arg0, 15
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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call void @use(i32 %quot_or_rem)
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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define <4 x i1> @ceil_shift4_v4i32(<4 x i32> %arg0) {
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; CHECK-LABEL: define <4 x i1> @ceil_shift4_v4i32(
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; CHECK-SAME: <4 x i32> [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr <4 x i32> [[ARG0]], splat (i32 16)
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[ARG0]], splat (i32 65535)
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext <4 x i1> [[HAS_REM]] to <4 x i32>
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or <4 x i32> [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[QUOT_OR_REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[TMP1]]
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;
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%quot = lshr <4 x i32> %arg0, splat (i32 16)
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%rem = and <4 x i32> %arg0, splat (i32 65535)
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%has_rem = icmp ne <4 x i32> %rem, zeroinitializer
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%zext_has_rem = zext <4 x i1> %has_rem to <4 x i32>
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%quot_or_rem = or <4 x i32> %quot, %zext_has_rem
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%res = icmp eq <4 x i32> %quot_or_rem, zeroinitializer
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ret <4 x i1> %res
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}
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define <8 x i1> @ceil_shift4_v8i16(<8 x i16> %arg0) {
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; CHECK-LABEL: define <8 x i1> @ceil_shift4_v8i16(
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; CHECK-SAME: <8 x i16> [[ARG0:%.*]]) {
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; CHECK-NEXT: [[QUOT:%.*]] = lshr <8 x i16> [[ARG0]], splat (i16 4)
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; CHECK-NEXT: [[REM:%.*]] = and <8 x i16> [[ARG0]], splat (i16 15)
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; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne <8 x i16> [[REM]], zeroinitializer
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; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext <8 x i1> [[HAS_REM]] to <8 x i16>
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; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or <8 x i16> [[QUOT]], [[ZEXT_HAS_REM]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <8 x i16> [[QUOT_OR_REM]], zeroinitializer
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; CHECK-NEXT: ret <8 x i1> [[TMP1]]
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;
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%quot = lshr <8 x i16> %arg0, splat (i16 4)
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%rem = and <8 x i16> %arg0, splat (i16 15)
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%has_rem = icmp ne <8 x i16> %rem, zeroinitializer
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%zext_has_rem = zext <8 x i1> %has_rem to <8 x i16>
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%quot_or_rem = or <8 x i16> %quot, %zext_has_rem
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%res = icmp eq <8 x i16> %quot_or_rem, zeroinitializer
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ret <8 x i1> %res
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}
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; negative tests
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define i1 @ceil_shift_not_mask_1(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift_not_mask_1(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 31
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%quot = lshr i32 %arg0, 4
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%rem = and i32 %arg0, 31
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}
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define i1 @ceil_shift_not_mask_2(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift_not_mask_2(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 5
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%quot = lshr i32 %arg0, 5
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%rem = and i32 %arg0, 15
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%has_rem = icmp ne i32 %rem, 0
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%zext_has_rem = zext i1 %has_rem to i32
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%quot_or_rem = or i32 %quot, %zext_has_rem
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%res = icmp eq i32 %quot_or_rem, 0
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ret i1 %res
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}

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