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Revert "reimplement the second half of the or/add optimization. We should now",
which depends on r116007, which I am about to revert. llvm-svn: 116031
1 parent ba66a81 commit efdf08b

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+20
-87
lines changed

4 files changed

+20
-87
lines changed

‎llvm/lib/Target/X86/X86InstrCompiler.td

Lines changed: 14 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1036,34 +1036,21 @@ def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
10361036
def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
10371037
"", // orq/addq REG, REG
10381038
[(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1039-
1040-
1041-
def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1042-
"", // orw/addw REG, imm
1043-
[(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1044-
def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1045-
"", // orl/addl REG, imm
1046-
[(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1047-
def ADD64ri32_DB : I<0, Pseudo,
1048-
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1049-
"", // orq/addq REG, imm
1050-
[(set GR64:$dst, (or_is_add GR64:$src1,
1051-
i64immSExt32:$src2))]>;
1052-
1053-
def ADD16ri8_DB : I<0, Pseudo,
1054-
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1055-
"", // orw/addw REG, imm8
1056-
[(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1057-
def ADD32ri8_DB : I<0, Pseudo,
1058-
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1059-
"", // orl/addl REG, imm8
1060-
[(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1061-
def ADD64ri8_DB : I<0, Pseudo,
1062-
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1063-
"", // orq/addq REG, imm8
1064-
[(set GR64:$dst, (or_is_add GR64:$src1,
1065-
i64immSExt8:$src2))]>;
10661039
}
1040+
1041+
def : Pat<(or_is_add GR16:$src1, imm:$src2),
1042+
(ADD16ri GR16:$src1, imm:$src2)>;
1043+
def : Pat<(or_is_add GR32:$src1, imm:$src2),
1044+
(ADD32ri GR32:$src1, imm:$src2)>;
1045+
def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
1046+
(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1047+
1048+
def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
1049+
(ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1050+
def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
1051+
(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1052+
def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
1053+
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
10671054
} // AddedComplexity
10681055

10691056

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -68,20 +68,14 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
6868
{ X86::ADC64rr, X86::ADC64mr },
6969
{ X86::ADD16ri, X86::ADD16mi },
7070
{ X86::ADD16ri8, X86::ADD16mi8 },
71-
{ X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE },
72-
{ X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE },
7371
{ X86::ADD16rr, X86::ADD16mr },
7472
{ X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE },
7573
{ X86::ADD32ri, X86::ADD32mi },
7674
{ X86::ADD32ri8, X86::ADD32mi8 },
77-
{ X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE },
78-
{ X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE },
7975
{ X86::ADD32rr, X86::ADD32mr },
8076
{ X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE },
8177
{ X86::ADD64ri32, X86::ADD64mi32 },
8278
{ X86::ADD64ri8, X86::ADD64mi8 },
83-
{ X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE },
84-
{ X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE },
8579
{ X86::ADD64rr, X86::ADD64mr },
8680
{ X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE },
8781
{ X86::ADD8ri, X86::ADD8mi },
@@ -1166,8 +1160,6 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
11661160
break;
11671161
case X86::ADD16ri:
11681162
case X86::ADD16ri8:
1169-
case X86::ADD16ri_DB:
1170-
case X86::ADD16ri8_DB:
11711163
addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
11721164
break;
11731165
case X86::ADD16rr:
@@ -1432,18 +1424,14 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
14321424
}
14331425
case X86::ADD64ri32:
14341426
case X86::ADD64ri8:
1435-
case X86::ADD64ri32_DB:
1436-
case X86::ADD64ri8_DB:
14371427
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
14381428
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
14391429
.addReg(Dest, RegState::Define |
14401430
getDeadRegState(isDead)),
14411431
Src, isKill, MI->getOperand(2).getImm());
14421432
break;
14431433
case X86::ADD32ri:
1444-
case X86::ADD32ri8:
1445-
case X86::ADD32ri_DB:
1446-
case X86::ADD32ri8_DB: {
1434+
case X86::ADD32ri8: {
14471435
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
14481436
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
14491437
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
@@ -1454,8 +1442,6 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
14541442
}
14551443
case X86::ADD16ri:
14561444
case X86::ADD16ri8:
1457-
case X86::ADD16ri_DB:
1458-
case X86::ADD16ri8_DB:
14591445
if (DisableLEA16)
14601446
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
14611447
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");

‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -437,15 +437,9 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
437437
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
438438
// this with an ugly goto in case the resultant OR uses EAX and needs the
439439
// short form.
440-
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
441-
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
442-
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
443-
case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
444-
case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
445-
case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
446-
case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
447-
case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
448-
case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
440+
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
441+
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
442+
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
449443

450444
// The assembler backend wants to see branches in their small form and relax
451445
// them to their large form. The JIT can only handle the large form because

‎llvm/test/CodeGen/X86/3addr-or.ll

Lines changed: 2 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
22
; rdar://7527734
33

4-
define i32 @test1(i32 %x) nounwind readnone ssp {
4+
define i32 @test(i32 %x) nounwind readnone ssp {
55
entry:
6-
; CHECK: test1:
6+
; CHECK: test:
77
; CHECK: leal 3(%rdi), %eax
88
%0 = shl i32 %x, 5 ; <i32> [#uses=1]
99
%1 = or i32 %0, 3 ; <i32> [#uses=1]
@@ -25,37 +25,3 @@ define i64 @test2(i8 %A, i8 %B) nounwind {
2525
%H = or i64 %G, %E ; <i64> [#uses=1]
2626
ret i64 %H
2727
}
28-
29-
;; Test that OR is only emitted as LEA, not as ADD.
30-
31-
define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
32-
entry:
33-
; No reason to emit an add here, should be an or.
34-
; CHECK: test3:
35-
; CHECK: orl $3, %edi
36-
%0 = shl i32 %x, 5
37-
%1 = or i32 %0, 3
38-
store i32 %1, i32* %P
39-
ret void
40-
}
41-
42-
define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
43-
entry:
44-
%and = and i32 %a, 6
45-
%and2 = and i32 %b, 16
46-
%or = or i32 %and2, %and
47-
ret i32 %or
48-
; CHECK: test4:
49-
; CHECK: leal (%rsi,%rdi), %eax
50-
}
51-
52-
define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp {
53-
entry:
54-
%and = and i32 %a, 6
55-
%and2 = and i32 %b, 16
56-
%or = or i32 %and2, %and
57-
store i32 %or, i32* %P, align 4
58-
ret void
59-
; CHECK: test5:
60-
; CHECK: orl
61-
}

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