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[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.
This addresses some failures I've seen in testing on real code.
1 parent 79682c4 commit eff60d8

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10 files changed

+150
-41
lines changed

10 files changed

+150
-41
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -282,14 +282,16 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
282282
};
283283

284284
LoadActions.legalForTypesWithMemDesc(
285-
{{s16, p0, s16, getScalarMemAlign(16)},
285+
{{s16, p0, s8, getScalarMemAlign(8)},
286286
{s32, p0, s8, getScalarMemAlign(8)},
287+
{s16, p0, s16, getScalarMemAlign(16)},
287288
{s32, p0, s16, getScalarMemAlign(16)},
288289
{s32, p0, s32, getScalarMemAlign(32)},
289290
{p0, p0, sXLen, getScalarMemAlign(XLen)}});
290291
StoreActions.legalForTypesWithMemDesc(
291-
{{s16, p0, s16, getScalarMemAlign(16)},
292+
{{s16, p0, s8, getScalarMemAlign(8)},
292293
{s32, p0, s8, getScalarMemAlign(8)},
294+
{s16, p0, s16, getScalarMemAlign(16)},
293295
{s32, p0, s16, getScalarMemAlign(16)},
294296
{s32, p0, s32, getScalarMemAlign(32)},
295297
{p0, p0, sXLen, getScalarMemAlign(XLen)}});
@@ -383,10 +385,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
383385

384386
LoadActions.widenScalarToNextPow2(0, /* MinSize = */ 8)
385387
.lowerIfMemSizeNotByteSizePow2()
386-
.clampScalar(0, s32, sXLen)
388+
.clampScalar(0, s16, sXLen)
387389
.lower();
388390
StoreActions
389-
.clampScalar(0, s32, sXLen)
391+
.clampScalar(0, s16, sXLen)
390392
.lowerIfMemSizeNotByteSizePow2()
391393
.lower();
392394

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,9 @@ def : StPat<store, SD, GPR, PtrVT>;
174174
def : LdPat<load, LH, i16>;
175175
def : StPat<store, SH, GPR, i16>;
176176

177+
def : LdPat<extloadi8, LBU, i16>; // Prefer unsigned due to no c.lb in Zcb.
178+
def : StPat<truncstorei8, SB, GPR, i16>;
179+
177180
//===----------------------------------------------------------------------===//
178181
// RV64 i32 patterns not used by SelectionDAG
179182
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,29 @@ body: |
4545
$x10 = COPY %1(s32)
4646
PseudoRET implicit $x10
4747
48+
...
49+
---
50+
name: load_i8_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10
57+
58+
; CHECK-LABEL: name: load_i8_i16
59+
; CHECK: liveins: $x10
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
63+
; CHECK-NEXT: $x10 = COPY [[LBU]]
64+
; CHECK-NEXT: PseudoRET implicit $x10
65+
%0:gprb(p0) = COPY $x10
66+
%1:gprb(s16) = G_LOAD %0(p0) :: (load (s8))
67+
%2:gprb(s32) = G_ANYEXT %1
68+
$x10 = COPY %2(s32)
69+
PseudoRET implicit $x10
70+
4871
...
4972
---
5073
name: load_i16_i16

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,29 @@ body: |
4545
$x10 = COPY %1(s64)
4646
PseudoRET implicit $x10
4747
48+
...
49+
---
50+
name: load_i8_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10
57+
58+
; CHECK-LABEL: name: load_i8_i16
59+
; CHECK: liveins: $x10
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
63+
; CHECK-NEXT: $x10 = COPY [[LBU]]
64+
; CHECK-NEXT: PseudoRET implicit $x10
65+
%0:gprb(p0) = COPY $x10
66+
%1:gprb(s16) = G_LOAD %0(p0) :: (load (s8))
67+
%2:gprb(s64) = G_ANYEXT %1
68+
$x10 = COPY %2(s64)
69+
PseudoRET implicit $x10
70+
4871
...
4972
---
5073
name: load_i16_i16

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,29 @@ body: |
4545
G_STORE %0(s32), %1(p0) :: (store (s16))
4646
PseudoRET
4747
48+
...
49+
---
50+
name: store_i8_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10, $x11
57+
58+
; CHECK-LABEL: name: store_i8_i16
59+
; CHECK: liveins: $x10, $x11
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
63+
; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8))
64+
; CHECK-NEXT: PseudoRET
65+
%0:gprb(s32) = COPY $x10
66+
%1:gprb(p0) = COPY $x11
67+
%2:gprb(s16) = G_TRUNC %0
68+
G_STORE %2(s16), %1(p0) :: (store (s8))
69+
PseudoRET
70+
4871
...
4972
---
5073
name: store_i16_i16

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,29 @@ body: |
4545
G_STORE %0(s64), %1(p0) :: (store (s16))
4646
PseudoRET
4747
48+
...
49+
---
50+
name: store_i8_i16
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.0:
56+
liveins: $x10, $x11
57+
58+
; CHECK-LABEL: name: store_i8_i16
59+
; CHECK: liveins: $x10, $x11
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
63+
; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8))
64+
; CHECK-NEXT: PseudoRET
65+
%0:gprb(s64) = COPY $x10
66+
%1:gprb(p0) = COPY $x11
67+
%2:gprb(s16) = G_TRUNC %0
68+
G_STORE %2(s16), %1(p0) :: (store (s8))
69+
PseudoRET
70+
4871
...
4972
---
5073
name: store_i16_i16

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,16 +25,18 @@ body: |
2525
; CHECK: liveins: $x10
2626
; CHECK-NEXT: {{ $}}
2727
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
28-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
29-
; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
28+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8))
29+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
30+
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32)
3031
; CHECK-NEXT: PseudoRET implicit $x10
3132
;
3233
; UNALIGNED-LABEL: name: load_i8
3334
; UNALIGNED: liveins: $x10
3435
; UNALIGNED-NEXT: {{ $}}
3536
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
36-
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
37-
; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32)
37+
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8))
38+
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
39+
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32)
3840
; UNALIGNED-NEXT: PseudoRET implicit $x10
3941
%0:_(p0) = COPY $x10
4042
%1:_(s8) = G_LOAD %0(p0) :: (load (s8))
@@ -231,9 +233,10 @@ body: |
231233
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
232234
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
233235
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
234-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
236+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
235237
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
236-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
238+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
239+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[C1]](s32)
237240
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
238241
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
239242
; CHECK-NEXT: PseudoRET implicit $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,17 +25,17 @@ body: |
2525
; CHECK: liveins: $x10
2626
; CHECK-NEXT: {{ $}}
2727
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
28-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
29-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
28+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8))
29+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
3030
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
3131
; CHECK-NEXT: PseudoRET implicit $x10
3232
;
3333
; UNALIGNED-LABEL: name: load_i8
3434
; UNALIGNED: liveins: $x10
3535
; UNALIGNED-NEXT: {{ $}}
3636
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
37-
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
38-
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
37+
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8))
38+
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
3939
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64)
4040
; UNALIGNED-NEXT: PseudoRET implicit $x10
4141
%0:_(p0) = COPY $x10
@@ -274,9 +274,9 @@ body: |
274274
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
275275
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
276276
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
277-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
277+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
278278
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
279-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
279+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
280280
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64)
281281
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
282282
; CHECK-NEXT: $x10 = COPY [[OR]](s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,17 @@ body: |
2626
; CHECK-NEXT: {{ $}}
2727
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
2828
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
29-
; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s8))
29+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
30+
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8))
3031
; CHECK-NEXT: PseudoRET
3132
;
3233
; UNALIGNED-LABEL: name: store_i8
3334
; UNALIGNED: liveins: $x10, $x11
3435
; UNALIGNED-NEXT: {{ $}}
3536
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
3637
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
37-
; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s8))
38+
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
39+
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8))
3840
; UNALIGNED-NEXT: PseudoRET
3941
%2:_(s32) = COPY $x10
4042
%0:_(s8) = G_TRUNC %2(s32)
@@ -228,15 +230,18 @@ body: |
228230
; CHECK: liveins: $x10, $x11
229231
; CHECK-NEXT: {{ $}}
230232
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
233+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
231234
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
235+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
232236
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
233237
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
234238
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
235239
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
240+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
236241
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
237242
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s32)
238-
; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s8))
239-
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1)
243+
; CHECK-NEXT: G_STORE [[COPY2]](s16), [[COPY1]](p0) :: (store (s8))
244+
; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1)
240245
; CHECK-NEXT: PseudoRET
241246
;
242247
; UNALIGNED-LABEL: name: store_i16_unaligned
@@ -280,19 +285,23 @@ body: |
280285
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
281286
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
282287
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s32)
288+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
283289
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
284290
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
285291
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
286292
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32)
293+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
287294
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
288295
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C4]](s32)
289-
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s8))
290-
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1)
296+
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8))
297+
; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1)
298+
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
291299
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
292300
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C5]](s32)
301+
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
293302
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C4]](s32)
294-
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2)
295-
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3)
303+
; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2)
304+
; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3)
296305
; CHECK-NEXT: PseudoRET
297306
;
298307
; UNALIGNED-LABEL: name: store_i32_unaligned

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -26,17 +26,17 @@ body: |
2626
; CHECK-NEXT: {{ $}}
2727
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
2828
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
29-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
30-
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s8))
29+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
30+
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8))
3131
; CHECK-NEXT: PseudoRET
3232
;
3333
; UNALIGNED-LABEL: name: store_i8
3434
; UNALIGNED: liveins: $x10, $x11
3535
; UNALIGNED-NEXT: {{ $}}
3636
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3737
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
38-
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
39-
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s8))
38+
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
39+
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8))
4040
; UNALIGNED-NEXT: PseudoRET
4141
%2:_(s64) = COPY $x10
4242
%0:_(s8) = G_TRUNC %2(s64)
@@ -259,17 +259,18 @@ body: |
259259
; CHECK: liveins: $x10, $x11
260260
; CHECK-NEXT: {{ $}}
261261
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
262+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
262263
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
263-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
264+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
264265
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
265266
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
266267
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
267268
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64)
269+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
268270
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
269271
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
270-
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s8))
271-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
272-
; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1)
272+
; CHECK-NEXT: G_STORE [[COPY2]](s16), [[COPY1]](p0) :: (store (s8))
273+
; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1)
273274
; CHECK-NEXT: PseudoRET
274275
;
275276
; UNALIGNED-LABEL: name: store_i16_unaligned
@@ -308,32 +309,31 @@ body: |
308309
; CHECK: liveins: $x10, $x11
309310
; CHECK-NEXT: {{ $}}
310311
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
311-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
312312
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
313-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
314313
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
315314
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
316315
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
317316
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64)
318-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
319317
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
320318
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
319+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
321320
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
322321
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
323322
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C4]]
324323
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C3]](s64)
324+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s64)
325325
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
326326
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C5]](s64)
327-
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s8))
328-
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
329-
; CHECK-NEXT: G_STORE [[TRUNC2]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1)
327+
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8))
328+
; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1)
329+
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
330330
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
331331
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C4]]
332332
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C6]](s64)
333+
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s64)
333334
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C5]](s64)
334-
; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2)
335-
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR2]](s64)
336-
; CHECK-NEXT: G_STORE [[TRUNC3]](s32), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3)
335+
; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2)
336+
; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3)
337337
; CHECK-NEXT: PseudoRET
338338
;
339339
; UNALIGNED-LABEL: name: store_i32_unaligned

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