[X86] Avoid crashing in PIC mode on narrowing to i8 followed by extention to i32

Author: Ralender

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

@@ -631,7 +631,8 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
 void
 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
                                      VRBaseMapType &VRBaseMap) {
-  Register VReg = getVR(Node->getOperand(0), VRBaseMap);
+  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
+  unsigned VReg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
 
   // Create the new VReg in the destination class and emit a copy.
   unsigned DstRCIdx = Node->getConstantOperandVal(1);

llvm/test/CodeGen/X86/x86-access-to-global.ll

@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -relocation-model=pic < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+@.str = external dso_local global i32
+
+define i1 @test() {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    calll .L0$pb
+; CHECK-NEXT:    .cfi_adjust_cfa_offset 4
+; CHECK-NEXT:  .L0$pb:
+; CHECK-NEXT:    popl %eax
+; CHECK-NEXT:    .cfi_adjust_cfa_offset -4
+; CHECK-NEXT:  .Ltmp0:
+; CHECK-NEXT:    addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
+; CHECK-NEXT:    movl $.str@GOTOFF, %ecx
+; CHECK-NEXT:    addb %al, %cl
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    retl
+  %i = ptrtoint ptr @.str to i8
+  %p = zext i8 %i to i32
+  %c = icmp eq i32 %p, 0
+  ret i1 %c
+}