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[RISCV] Increase GPRPair Allocation Priority
This echoes what has been done for the lmul>1 vector registers, increasing priority for pairs compared to single GPRs. The changes here are not particularly large, in part due to the fact that GPRPairs are not generated in many examples, but there look to be small savings in the number of register pair copies (where instead a GPR is copied).
1 parent f15fbd1 commit f072c08

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9 files changed

+150
-151
lines changed

9 files changed

+150
-151
lines changed

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -358,7 +358,7 @@ let RegAltNameIndices = [ABIRegAltName] in {
358358
}
359359
}
360360

361-
let RegInfos = XLenPairRI, CopyCost = 2 in {
361+
let RegInfos = XLenPairRI, CopyCost = 2, AllocationPriority = 1 in {
362362
def GPRPair : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
363363
X10_X11, X12_X13, X14_X15, X16_X17,
364364
X6_X7,
@@ -373,7 +373,7 @@ def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub GPRPair
373373
def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
374374
X10_X11, X12_X13, X14_X15, X8_X9
375375
)>;
376-
} // let RegInfos = XLenPairRI, CopyCost = 2
376+
} // let RegInfos = XLenPairRI, CopyCost = 2, AllocationPriority = 1
377377

378378
//===----------------------------------------------------------------------===//
379379
// Floating Point registers

‎llvm/test/CodeGen/RISCV/double-convert.ll‎

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -729,13 +729,13 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
729729
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
730730
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
731731
; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
732-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
733-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI12_0)(a2)
734-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI12_0)
735-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
732+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI12_0)
733+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a3)
734+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI12_0)
735+
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
736736
; RV32IZFINXZDINX-NEXT: mv s1, a1
737737
; RV32IZFINXZDINX-NEXT: mv s0, a0
738-
; RV32IZFINXZDINX-NEXT: fle.d s2, a4, s0
738+
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
739739
; RV32IZFINXZDINX-NEXT: call __fixdfdi
740740
; RV32IZFINXZDINX-NEXT: lui a3, 524288
741741
; RV32IZFINXZDINX-NEXT: lui a2, 524288
@@ -981,15 +981,15 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
981981
; RV32IZFINXZDINX-NEXT: mv s1, a1
982982
; RV32IZFINXZDINX-NEXT: mv s0, a0
983983
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
984-
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
984+
; RV32IZFINXZDINX-NEXT: fle.d a4, zero, s0
985985
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI14_0)
986-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a3)
986+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI14_0)(a3)
987987
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI14_0)
988-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a3)
989-
; RV32IZFINXZDINX-NEXT: neg a2, a2
990-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
991-
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
992-
; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
988+
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
989+
; RV32IZFINXZDINX-NEXT: neg a4, a4
990+
; RV32IZFINXZDINX-NEXT: and a0, a4, a0
991+
; RV32IZFINXZDINX-NEXT: and a1, a4, a1
992+
; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
993993
; RV32IZFINXZDINX-NEXT: neg a2, a2
994994
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
995995
; RV32IZFINXZDINX-NEXT: or a1, a2, a1
@@ -1650,17 +1650,17 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
16501650
;
16511651
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
16521652
; RV32IZFINXZDINX: # %bb.0: # %start
1653-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
1654-
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_1)
1655-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_0)(a2)
1656-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI26_0)
1657-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
1658-
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_1)(a3)
1659-
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_1)
1653+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_0)
1654+
; RV32IZFINXZDINX-NEXT: lui a5, %hi(.LCPI26_1)
1655+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a3)
1656+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_0)
16601657
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
1658+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a5)
1659+
; RV32IZFINXZDINX-NEXT: addi a5, a5, %lo(.LCPI26_1)
1660+
; RV32IZFINXZDINX-NEXT: lw a5, 4(a5)
16611661
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
1662-
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
1663-
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
1662+
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
1663+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
16641664
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
16651665
; RV32IZFINXZDINX-NEXT: neg a1, a6
16661666
; RV32IZFINXZDINX-NEXT: and a0, a1, a0
@@ -1848,12 +1848,12 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
18481848
;
18491849
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
18501850
; RV32IZFINXZDINX: # %bb.0: # %start
1851-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0)
1852-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI28_0)(a2)
1853-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI28_0)
1854-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
1851+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI28_0)
1852+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a3)
1853+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI28_0)
1854+
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
18551855
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero
1856-
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
1856+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
18571857
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
18581858
; RV32IZFINXZDINX-NEXT: ret
18591859
;
@@ -2026,17 +2026,17 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
20262026
;
20272027
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
20282028
; RV32IZFINXZDINX: # %bb.0: # %start
2029-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0)
2030-
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_1)
2031-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_0)(a2)
2032-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI30_0)
2033-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
2034-
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_1)(a3)
2035-
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_1)
2029+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_0)
2030+
; RV32IZFINXZDINX-NEXT: lui a5, %hi(.LCPI30_1)
2031+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a3)
2032+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_0)
20362033
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
2034+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a5)
2035+
; RV32IZFINXZDINX-NEXT: addi a5, a5, %lo(.LCPI30_1)
2036+
; RV32IZFINXZDINX-NEXT: lw a5, 4(a5)
20372037
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
2038-
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
2039-
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
2038+
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
2039+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
20402040
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
20412041
; RV32IZFINXZDINX-NEXT: neg a1, a6
20422042
; RV32IZFINXZDINX-NEXT: and a0, a1, a0
@@ -2224,12 +2224,12 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
22242224
;
22252225
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
22262226
; RV32IZFINXZDINX: # %bb.0: # %start
2227-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0)
2228-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI32_0)(a2)
2229-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI32_0)
2230-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
2227+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI32_0)
2228+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a3)
2229+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI32_0)
2230+
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
22312231
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero
2232-
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
2232+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
22332233
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
22342234
; RV32IZFINXZDINX-NEXT: ret
22352235
;

‎llvm/test/CodeGen/RISCV/double-imm.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -54,11 +54,11 @@ define double @double_imm_op(double %a) nounwind {
5454
;
5555
; CHECKRV32ZDINX-LABEL: double_imm_op:
5656
; CHECKRV32ZDINX: # %bb.0:
57-
; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0)
58-
; CHECKRV32ZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
59-
; CHECKRV32ZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
60-
; CHECKRV32ZDINX-NEXT: lw a5, 4(a2)
61-
; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a4
57+
; CHECKRV32ZDINX-NEXT: lui a3, %hi(.LCPI1_0)
58+
; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3)
59+
; CHECKRV32ZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0)
60+
; CHECKRV32ZDINX-NEXT: lw a3, 4(a3)
61+
; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a2
6262
; CHECKRV32ZDINX-NEXT: ret
6363
;
6464
; CHECKRV64ZDINX-LABEL: double_imm_op:

‎llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -286,15 +286,15 @@ define double @sincos_f64(double %a) nounwind strictfp {
286286
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
287287
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
288288
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
289-
; RV32IZFINXZDINX-NEXT: mv s0, a1
290-
; RV32IZFINXZDINX-NEXT: mv s1, a0
289+
; RV32IZFINXZDINX-NEXT: mv s2, a1
290+
; RV32IZFINXZDINX-NEXT: mv s3, a0
291291
; RV32IZFINXZDINX-NEXT: call sin
292-
; RV32IZFINXZDINX-NEXT: mv s2, a0
293-
; RV32IZFINXZDINX-NEXT: mv s3, a1
294-
; RV32IZFINXZDINX-NEXT: mv a0, s1
295-
; RV32IZFINXZDINX-NEXT: mv a1, s0
292+
; RV32IZFINXZDINX-NEXT: mv s0, a0
293+
; RV32IZFINXZDINX-NEXT: mv s1, a1
294+
; RV32IZFINXZDINX-NEXT: mv a0, s3
295+
; RV32IZFINXZDINX-NEXT: mv a1, s2
296296
; RV32IZFINXZDINX-NEXT: call cos
297-
; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
297+
; RV32IZFINXZDINX-NEXT: fadd.d a0, s0, a0
298298
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
299299
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
300300
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/double-intrinsics.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -241,15 +241,15 @@ define double @sincos_f64(double %a) nounwind {
241241
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
242242
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
243243
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
244-
; RV32IZFINXZDINX-NEXT: mv s0, a1
245-
; RV32IZFINXZDINX-NEXT: mv s1, a0
244+
; RV32IZFINXZDINX-NEXT: mv s2, a1
245+
; RV32IZFINXZDINX-NEXT: mv s3, a0
246246
; RV32IZFINXZDINX-NEXT: call sin
247-
; RV32IZFINXZDINX-NEXT: mv s2, a0
248-
; RV32IZFINXZDINX-NEXT: mv s3, a1
249-
; RV32IZFINXZDINX-NEXT: mv a0, s1
250-
; RV32IZFINXZDINX-NEXT: mv a1, s0
247+
; RV32IZFINXZDINX-NEXT: mv s0, a0
248+
; RV32IZFINXZDINX-NEXT: mv s1, a1
249+
; RV32IZFINXZDINX-NEXT: mv a0, s3
250+
; RV32IZFINXZDINX-NEXT: mv a1, s2
251251
; RV32IZFINXZDINX-NEXT: call cos
252-
; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
252+
; RV32IZFINXZDINX-NEXT: fadd.d a0, s0, a0
253253
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
254254
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
255255
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/double-mem.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -179,12 +179,12 @@ define dso_local double @fld_fsd_constant(double %a) nounwind {
179179
;
180180
; RV32IZFINXZDINX-LABEL: fld_fsd_constant:
181181
; RV32IZFINXZDINX: # %bb.0:
182-
; RV32IZFINXZDINX-NEXT: lui a2, 912092
183-
; RV32IZFINXZDINX-NEXT: lw a4, -273(a2)
184-
; RV32IZFINXZDINX-NEXT: lw a5, -269(a2)
185-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a4
186-
; RV32IZFINXZDINX-NEXT: sw a0, -273(a2)
187-
; RV32IZFINXZDINX-NEXT: sw a1, -269(a2)
182+
; RV32IZFINXZDINX-NEXT: lui a4, 912092
183+
; RV32IZFINXZDINX-NEXT: lw a2, -273(a4)
184+
; RV32IZFINXZDINX-NEXT: lw a3, -269(a4)
185+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
186+
; RV32IZFINXZDINX-NEXT: sw a0, -273(a4)
187+
; RV32IZFINXZDINX-NEXT: sw a1, -269(a4)
188188
; RV32IZFINXZDINX-NEXT: ret
189189
;
190190
; RV64IZFINXZDINX-LABEL: fld_fsd_constant:
@@ -198,10 +198,10 @@ define dso_local double @fld_fsd_constant(double %a) nounwind {
198198
;
199199
; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_constant:
200200
; RV32IZFINXZDINXZILSD: # %bb.0:
201-
; RV32IZFINXZDINXZILSD-NEXT: lui a2, 912092
202-
; RV32IZFINXZDINXZILSD-NEXT: ld a4, -273(a2)
203-
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a4
204-
; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a2)
201+
; RV32IZFINXZDINXZILSD-NEXT: lui a4, 912092
202+
; RV32IZFINXZDINXZILSD-NEXT: ld a2, -273(a4)
203+
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2
204+
; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a4)
205205
; RV32IZFINXZDINXZILSD-NEXT: ret
206206
%1 = inttoptr i32 3735928559 to ptr
207207
%2 = load volatile double, ptr %1

‎llvm/test/CodeGen/RISCV/double-previous-failure.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,18 +50,18 @@ define i32 @main() nounwind {
5050
; RV32IZFINXZDINX-NEXT: lui a1, 262144
5151
; RV32IZFINXZDINX-NEXT: li a0, 0
5252
; RV32IZFINXZDINX-NEXT: call test
53-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
54-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
55-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
56-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
57-
; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a4
53+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_0)
54+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3)
55+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0)
56+
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
57+
; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2
5858
; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3
5959
; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry
60-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
61-
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a2)
62-
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_1)
63-
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
64-
; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0
60+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_1)
61+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a3)
62+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_1)
63+
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
64+
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
6565
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
6666
; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
6767
; RV32IZFINXZDINX-NEXT: call exit

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