Skip to content

Commit f080cb1

Browse files
lenarysvs-quic
lenary
and
svs-quic
committed
[RISCV] Use Hints for Xqcisim/Xqcisync Aliases
My aim here is to make these a little easier to maintain by relying on aliases where these instructions overlap with the Hint instructions they are based on. The following instructions have not been converted to aliases as they have complex mappings from ther immediate encodings to the immediate encoding of the underlying instruction (setting high bits): - qc.pputci - qc.sync, qc.sync, qc.syncwf, qc.syncwl - qc.c.sync, qc.c.syncr, qc.c.syncwf, qc.syncwl Co-authored-by: Sudharsan Veeravalli <[email protected]>
1 parent ccc96e6 commit f080cb1

File tree

3 files changed

+48
-44
lines changed

3 files changed

+48
-44
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 23 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1120,27 +1120,11 @@ let Predicates = [HasVendorXqcisync, IsRV32] in {
11201120
def QC_C_SYNCWF : QCIRVInst16CBSYNC<0b100, "qc.c.syncwf">;
11211121
def QC_C_SYNCWL : QCIRVInst16CBSYNC<0b101, "qc.c.syncwl">;
11221122

1123-
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
1124-
def QC_C_DELAY : RVInst16CI<0b000, 0b10, (outs),
1125-
(ins uimm5nonzero:$imm),
1126-
"qc.c.delay", "$imm"> {
1127-
let Inst{12} = 0;
1128-
let Inst{11-7} = 0;
1129-
let Inst{6-2} = imm{4-0};
1130-
}
1123+
// qc.c.delay implemented as an alias, below
11311124
} // Predicates = [HasVendorXqcisync, IsRV32]
11321125

11331126
let Predicates = [HasVendorXqcisim, IsRV32] in {
11341127
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1135-
def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),
1136-
"qc.psyscalli", "$imm10"> {
1137-
bits<10> imm10;
1138-
1139-
let rs1 = 0;
1140-
let rd = 0;
1141-
let imm12 = {0b00, imm10};
1142-
}
1143-
11441128
def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
11451129
"qc.pputci", "$imm8"> {
11461130
bits<8> imm8;
@@ -1150,18 +1134,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
11501134
let imm12 = {0b0100, imm8};
11511135
}
11521136

1153-
def QC_PCOREDUMP : QCISim_NONE<0b0110, "qc.pcoredump">;
1154-
def QC_PPREGS : QCISim_NONE<0b0111, "qc.ppregs">;
1155-
def QC_PPREG : QCISim_RS1<0b1000, "qc.ppreg">;
1156-
def QC_PPUTC : QCISim_RS1<0b1001, "qc.pputc">;
1157-
def QC_PPUTS : QCISim_RS1<0b1010, "qc.pputs">;
1158-
def QC_PEXIT : QCISim_RS1<0b1011, "qc.pexit">;
1159-
def QC_PSYSCALL : QCISim_RS1<0b1100, "qc.psyscall">;
1160-
1161-
def QC_C_PTRACE : RVInst16CI<0b000, 0b10, (outs), (ins), "qc.c.ptrace", ""> {
1162-
let rd = 0;
1163-
let imm = 0;
1164-
}
1137+
// The other instructions are all implemented as aliases, below
11651138
} // mayLoad = 0, mayStore = 0, hasSideEffects = 1
11661139
} // Predicates = [HasVendorXqcisim, IsRV32]
11671140

@@ -1218,6 +1191,27 @@ let EmitPriority = 0 in {
12181191
} // EmitPriority = 0
12191192
} // Predicates = [HasVendorXqcilo, IsRV32]
12201193

1194+
let Predicates = [HasVendorXqcisim, IsRV32] in {
1195+
let EmitPriority = 1 in {
1196+
def : InstAlias<"qc.c.ptrace", (C_SLLI X0, 0)>;
1197+
1198+
def : InstAlias<"qc.psyscalli $imm", (SLTI X0, X0, uimm10:$imm)>;
1199+
def : InstAlias<"qc.pcoredump", (SLTI X0, X0, 1536)>;
1200+
def : InstAlias<"qc.ppregs", (SLTI X0, X0, 1792)>;
1201+
def : InstAlias<"qc.ppreg $rs1", (SLTI X0, GPR:$rs1, -2048)>;
1202+
def : InstAlias<"qc.pputc $rs1", (SLTI X0, GPR:$rs1, -1792)>;
1203+
def : InstAlias<"qc.pputs $rs1", (SLTI X0, GPR:$rs1, -1536)>;
1204+
def : InstAlias<"qc.pexit $rs1", (SLTI X0, GPR:$rs1, -1280)>;
1205+
def : InstAlias<"qc.psyscall $rs1", (SLTI X0, GPR:$rs1, -1024)>;
1206+
} // EmitPriority = 1
1207+
} // Predicates = [HasVendorXqcisim, IsRV32]
1208+
1209+
let Predicates = [HasVendorXqcisync, IsRV32] in {
1210+
let EmitPriority = 1 in {
1211+
def : InstAlias<"qc.c.delay $imm", (C_SLLI X0, uimm5nonzero:$imm)>;
1212+
}
1213+
} // Predicates = [HasVendorXqcisync, IsRV32]
1214+
12211215
//===----------------------------------------------------------------------===//
12221216
// Pseudo-instructions
12231217
//===----------------------------------------------------------------------===//

‎llvm/test/MC/RISCV/xqcisim-valid.s‎

Lines changed: 21 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3,50 +3,59 @@
33
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
44
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
55
# RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \
6-
# RUN: | FileCheck -check-prefix=CHECK-INST %s
6+
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s
77
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -show-encoding \
8-
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
8+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
99
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
1010
# RUN: | llvm-objdump --mattr=+experimental-xqcisim --no-print-imm-hex -d - \
11-
# RUN: | FileCheck -check-prefix=CHECK-INST %s
11+
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s
1212

1313

14-
# CHECK-INST: qc.psyscalli 1023
14+
# CHECK-ALIAS: qc.psyscalli 1023
15+
# CHECK-NOINST: slti zero, zero, 1023
1516
# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x3f]
1617
qc.psyscalli 1023
1718

1819
# CHECK-INST: qc.pputci 255
1920
# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x4f]
2021
qc.pputci 255
2122

22-
# CHECK-INST: qc.c.ptrace
23+
# CHECK-ALIAS: qc.c.ptrace
24+
# CHECK-NOALIAS: c.slli zero, 0
2325
# CHECK-ENC: encoding: [0x02,0x00]
2426
qc.c.ptrace
2527

26-
# CHECK-INST: qc.pcoredump
28+
# CHECK-ALIAS: qc.pcoredump
29+
# CHECK-NOALIAS: slti zero, zero, 1536
2730
# CHECK-ENC: encoding: [0x13,0x20,0x00,0x60]
2831
qc.pcoredump
2932

30-
# CHECK-INST: qc.ppregs
33+
# CHECK-ALIAS: qc.ppregs
34+
# CHECK-NOALIAS: slti zero, zero, 1792
3135
# CHECK-ENC: encoding: [0x13,0x20,0x00,0x70]
3236
qc.ppregs
3337

34-
# CHECK-INST: qc.ppreg a0
38+
# CHECK-ALIAS: qc.ppreg a0
39+
# CHECK-NOALIAS: slti zero, a0, -2048
3540
# CHECK-ENC: encoding: [0x13,0x20,0x05,0x80]
3641
qc.ppreg x10
3742

38-
# CHECK-INST: qc.pputc t2
43+
# CHECK-ALIAS: qc.pputc t2
44+
# CHECK-NOALIAS: slti zero, t2, -1792
3945
# CHECK-ENC: encoding: [0x13,0xa0,0x03,0x90]
4046
qc.pputc x7
4147

42-
# CHECK-INST: qc.pputs a5
48+
# CHECK-ALIAS: qc.pputs a5
49+
# CHECK-NOALIAS: slti zero, a5, -1536
4350
# CHECK-ENC: encoding: [0x13,0xa0,0x07,0xa0]
4451
qc.pputs x15
4552

46-
# CHECK-INST: qc.pexit s10
53+
# CHECK-ALIAS: qc.pexit s10
54+
# CHECK-NOALIAS: slti zero, s10, -1280
4755
# CHECK-ENC: encoding: [0x13,0x20,0x0d,0xb0]
4856
qc.pexit x26
4957

50-
# CHECK-INST: qc.psyscall a1
58+
# CHECK-ALIAS: qc.psyscall a1
59+
# CHECK-NOALIAS: slti zero, a1, -1024
5160
# CHECK-ENC: encoding: [0x13,0xa0,0x05,0xc0]
5261
qc.psyscall x11

‎llvm/test/MC/RISCV/xqcisync-valid.s‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,14 +3,15 @@
33
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
44
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
55
# RUN: | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \
6-
# RUN: | FileCheck -check-prefix=CHECK-INST %s
6+
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s
77
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -show-encoding \
88
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
99
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
1010
# RUN: | llvm-objdump --mattr=+experimental-xqcisync --no-print-imm-hex -d - \
11-
# RUN: | FileCheck -check-prefix=CHECK-INST %s
11+
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s
1212

13-
# CHECK-INST: qc.c.delay 10
13+
# CHECK-NOALIAS: c.slli zero, 10
14+
# CHECK-ALIAS: qc.c.delay 10
1415
# CHECK-ENC: encoding: [0x2a,0x00]
1516
qc.c.delay 10
1617

0 commit comments

Comments
 (0)