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[RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal interleaved access (#115257)
This is another piece split off from the work to add zvfhmin/zvfbfmin to isLegalElementTypeForRVV. This is needed to get InterleavedAccessPass to lower [de]interleaves to segment load/stores.
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5 files changed

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-9
lines changed

5 files changed

+154
-9
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21509,7 +21509,12 @@ bool RISCVTargetLowering::isLegalInterleavedAccessType(
2150921509
if (!isTypeLegal(VT))
2151021510
return false;
2151121511

21512-
if (!isLegalElementTypeForRVV(VT.getScalarType()) ||
21512+
// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
21513+
if (!(isLegalElementTypeForRVV(VT.getScalarType()) ||
21514+
(VT.getScalarType() == MVT::bf16 &&
21515+
Subtarget.hasVInstructionsBF16Minimal()) ||
21516+
(VT.getScalarType() == MVT::f16 &&
21517+
Subtarget.hasVInstructionsF16Minimal())) ||
2151321518
!allowsMemoryAccessForAlignment(VTy->getContext(), DL, VT, AddrSpace,
2151421519
Alignment))
2151521520
return false;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll‎

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s
3-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s
2+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s
3+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s
4+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s
5+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s
46

57
; Integers
68

@@ -107,6 +109,28 @@ declare {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64>)
107109

108110
; Floats
109111

112+
define {<2 x bfloat>, <2 x bfloat>} @vector_deinterleave_load_v2bf16_v4bf16(ptr %p) {
113+
; CHECK-LABEL: vector_deinterleave_load_v2bf16_v4bf16:
114+
; CHECK: # %bb.0:
115+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
116+
; CHECK-NEXT: vlseg2e16.v v8, (a0)
117+
; CHECK-NEXT: ret
118+
%vec = load <4 x bfloat>, ptr %p
119+
%retval = call {<2 x bfloat>, <2 x bfloat>} @llvm.vector.deinterleave2.v4bf16(<4 x bfloat> %vec)
120+
ret {<2 x bfloat>, <2 x bfloat>} %retval
121+
}
122+
123+
define {<4 x bfloat>, <4 x bfloat>} @vector_deinterleave_load_v4bf16_v8bf16(ptr %p) {
124+
; CHECK-LABEL: vector_deinterleave_load_v4bf16_v8bf16:
125+
; CHECK: # %bb.0:
126+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
127+
; CHECK-NEXT: vlseg2e16.v v8, (a0)
128+
; CHECK-NEXT: ret
129+
%vec = load <8 x bfloat>, ptr %p
130+
%retval = call {<4 x bfloat>, <4 x bfloat>} @llvm.vector.deinterleave2.v8bf16(<8 x bfloat> %vec)
131+
ret {<4 x bfloat>, <4 x bfloat>} %retval
132+
}
133+
110134
define {<2 x half>, <2 x half>} @vector_deinterleave_load_v2f16_v4f16(ptr %p) {
111135
; CHECK-LABEL: vector_deinterleave_load_v2f16_v4f16:
112136
; CHECK: # %bb.0:
@@ -140,6 +164,17 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_load_v2f32_v4f32(ptr %p)
140164
ret {<2 x float>, <2 x float>} %retval
141165
}
142166

167+
define {<8 x bfloat>, <8 x bfloat>} @vector_deinterleave_load_v8bf16_v16bf16(ptr %p) {
168+
; CHECK-LABEL: vector_deinterleave_load_v8bf16_v16bf16:
169+
; CHECK: # %bb.0:
170+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
171+
; CHECK-NEXT: vlseg2e16.v v8, (a0)
172+
; CHECK-NEXT: ret
173+
%vec = load <16 x bfloat>, ptr %p
174+
%retval = call {<8 x bfloat>, <8 x bfloat>} @llvm.vector.deinterleave2.v16bf16(<16 x bfloat> %vec)
175+
ret {<8 x bfloat>, <8 x bfloat>} %retval
176+
}
177+
143178
define {<8 x half>, <8 x half>} @vector_deinterleave_load_v8f16_v16f16(ptr %p) {
144179
; CHECK-LABEL: vector_deinterleave_load_v8f16_v16f16:
145180
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll‎

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s
3-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s
2+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s
3+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s
4+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s
5+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s
46

57
; Integers
68

@@ -85,6 +87,28 @@ declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
8587

8688
; Floats
8789

90+
define void @vector_interleave_store_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, ptr %p) {
91+
; CHECK-LABEL: vector_interleave_store_v4bf16_v2bf16:
92+
; CHECK: # %bb.0:
93+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
94+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
95+
; CHECK-NEXT: ret
96+
%res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
97+
store <4 x bfloat> %res, ptr %p
98+
ret void
99+
}
100+
101+
define void @vector_interleave_store_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, ptr %p) {
102+
; CHECK-LABEL: vector_interleave_store_v8bf16_v4bf16:
103+
; CHECK: # %bb.0:
104+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
105+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
106+
; CHECK-NEXT: ret
107+
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
108+
store <8 x bfloat> %res, ptr %p
109+
ret void
110+
}
111+
88112
define void @vector_interleave_store_v4f16_v2f16(<2 x half> %a, <2 x half> %b, ptr %p) {
89113
; CHECK-LABEL: vector_interleave_store_v4f16_v2f16:
90114
; CHECK: # %bb.0:
@@ -118,6 +142,17 @@ define void @vector_interleave_store_v4f32_v2f32(<2 x float> %a, <2 x float> %b,
118142
ret void
119143
}
120144

145+
define void @vector_interleave_store_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, ptr %p) {
146+
; CHECK-LABEL: vector_interleave_store_v16bf16_v8bf16:
147+
; CHECK: # %bb.0:
148+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
149+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
150+
; CHECK-NEXT: ret
151+
%res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
152+
store <16 x bfloat> %res, ptr %p
153+
ret void
154+
}
155+
121156
define void @vector_interleave_store_v16f16_v8f16(<8 x half> %a, <8 x half> %b, ptr %p) {
122157
; CHECK-LABEL: vector_interleave_store_v16f16_v8f16:
123158
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll‎

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV32 %s
3-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV64 %s
2+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV32 %s
3+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV64 %s
4+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV32 %s
5+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV64 %s
46

57
; Integers
68

@@ -199,6 +201,28 @@ declare {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv1
199201

200202
; Floats
201203

204+
define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_load_nxv2bf16_nxv4bf16(ptr %p) {
205+
; CHECK-LABEL: vector_deinterleave_load_nxv2bf16_nxv4bf16:
206+
; CHECK: # %bb.0:
207+
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
208+
; CHECK-NEXT: vlseg2e16.v v8, (a0)
209+
; CHECK-NEXT: ret
210+
%vec = load <vscale x 4 x bfloat>, ptr %p
211+
%retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
212+
ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
213+
}
214+
215+
define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_load_nxv4bf16_nxv8bf16(ptr %p) {
216+
; CHECK-LABEL: vector_deinterleave_load_nxv4bf16_nxv8bf16:
217+
; CHECK: # %bb.0:
218+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
219+
; CHECK-NEXT: vlseg2e16.v v8, (a0)
220+
; CHECK-NEXT: ret
221+
%vec = load <vscale x 8 x bfloat>, ptr %p
222+
%retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
223+
ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
224+
}
225+
202226
define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_load_nxv2f16_nxv4f16(ptr %p) {
203227
; CHECK-LABEL: vector_deinterleave_load_nxv2f16_nxv4f16:
204228
; CHECK: # %bb.0:
@@ -232,6 +256,17 @@ define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_load_nx
232256
ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
233257
}
234258

259+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_load_nxv8bf16_nxv16bf16(ptr %p) {
260+
; CHECK-LABEL: vector_deinterleave_load_nxv8bf16_nxv16bf16:
261+
; CHECK: # %bb.0:
262+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
263+
; CHECK-NEXT: vlseg2e16.v v8, (a0)
264+
; CHECK-NEXT: ret
265+
%vec = load <vscale x 16 x bfloat>, ptr %p
266+
%retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
267+
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
268+
}
269+
235270
define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_load_nxv8f16_nxv16f16(ptr %p) {
236271
; CHECK-LABEL: vector_deinterleave_load_nxv8f16_nxv16f16:
237272
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll‎

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck --check-prefixes=CHECK,RV32 %s
3-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck --check-prefixes=CHECK,RV64 %s
2+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV32 %s
3+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV64 %s
4+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV32 %s
5+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV64 %s
46

57
; Integers
68

@@ -154,6 +156,28 @@ declare <vscale x 16 x i64> @llvm.vector.interleave2.nxv16i64(<vscale x 8 x i64>
154156

155157
; Floats
156158

159+
define void @vector_interleave_store_nxv4bf16_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, ptr %p) {
160+
; CHECK-LABEL: vector_interleave_store_nxv4bf16_nxv2bf16:
161+
; CHECK: # %bb.0:
162+
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
163+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
164+
; CHECK-NEXT: ret
165+
%res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
166+
store <vscale x 4 x bfloat> %res, ptr %p
167+
ret void
168+
}
169+
170+
define void @vector_interleave_store_nxv8bf16_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, ptr %p) {
171+
; CHECK-LABEL: vector_interleave_store_nxv8bf16_nxv4bf16:
172+
; CHECK: # %bb.0:
173+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
174+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
175+
; CHECK-NEXT: ret
176+
%res = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)
177+
store <vscale x 8 x bfloat> %res, ptr %p
178+
ret void
179+
}
180+
157181
define void @vector_interleave_store_nxv4f16_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, ptr %p) {
158182
; CHECK-LABEL: vector_interleave_store_nxv4f16_nxv2f16:
159183
; CHECK: # %bb.0:
@@ -187,6 +211,17 @@ define void @vector_interleave_store_nxv4f32_nxv2f32(<vscale x 2 x float> %a, <v
187211
ret void
188212
}
189213

214+
define void @vector_interleave_store_nxv16bf16_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, ptr %p) {
215+
; CHECK-LABEL: vector_interleave_store_nxv16bf16_nxv8bf16:
216+
; CHECK: # %bb.0:
217+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
218+
; CHECK-NEXT: vsseg2e16.v v8, (a0)
219+
; CHECK-NEXT: ret
220+
%res = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
221+
store <vscale x 16 x bfloat> %res, ptr %p
222+
ret void
223+
}
224+
190225
define void @vector_interleave_store_nxv16f16_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, ptr %p) {
191226
; CHECK-LABEL: vector_interleave_store_nxv16f16_nxv8f16:
192227
; CHECK: # %bb.0:

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