Remove infinite recursion checking

Yui5427 · Yui5427 · commit f0e2a658f2db · 2025-09-06T18:56:24.000+08:00
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10001,25 +10001,15 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
     }
   }
 
-  // fold (not (sub Y, X)) -> (add X, ~Y) if Y is a constant or the subtract has
-  // a single use.
+  // fold (not (sub Y, X)) -> (add X, ~Y) if Y is a constant
   if (N0.getOpcode() == ISD::SUB && isAllOnesConstant(N1)) {
     SDValue Y = N0.getOperand(0);
     SDValue X = N0.getOperand(1);
 
-    // Avoid infinite recursion with
-    // Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z)))
-    if (none_of(N->users(),
-                [](SDNode *User) { return User->getOpcode() == ISD::AND; })) {
-      if (isa<ConstantSDNode>(Y) || N0.hasOneUse()) {
-        SDValue NotY = DAG.getNOT(DL, Y, VT);
-        return DAG.getNode(ISD::ADD, DL, VT, X, NotY, N->getFlags());
-      }
-    } else {
-      if (isa<ConstantSDNode>(Y) && N0.hasOneUse()) {
-        SDValue NotY = DAG.getNOT(DL, Y, VT);
-        return DAG.getNode(ISD::ADD, DL, VT, X, NotY, N->getFlags());
-      }
+    if (auto *YConst = dyn_cast<ConstantSDNode>(Y)) {
+      APInt NotYValue = ~YConst->getAPIntValue();
+      SDValue NotY = DAG.getConstant(NotYValue, DL, VT);
+      return DAG.getNode(ISD::ADD, DL, VT, X, NotY, N->getFlags());
     }
   }
 
diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -31,12 +31,12 @@ entry:
 define zeroext i1 @test2(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    lwz 3, 0(3)
-; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
-; CHECK-NEXT:    not 4, 4
-; CHECK-NEXT:    add 3, 3, 4
+; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    sub 3, 4, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rldicl 3, 3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -76,8 +76,8 @@ define zeroext i1 @test4(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
 ; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    add 3, 4, 3
 ; CHECK-NEXT:    rldicl 3, 3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -12,8 +12,8 @@
 define dso_local signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igeuc:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -65,9 +65,9 @@ entry:
 define dso_local void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igeuc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -12,8 +12,8 @@
 define dso_local signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igeui:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -64,9 +64,9 @@ entry:
 define dso_local void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igeui_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -12,8 +12,8 @@
 define dso_local signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igeus:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -64,9 +64,9 @@ entry:
 define dso_local void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igeus_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
@@ -12,8 +12,8 @@
 define dso_local signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ileuc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -67,9 +67,9 @@ entry:
 define dso_local void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ileuc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileui.ll b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
@@ -12,8 +12,8 @@
 define dso_local signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ileui:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -67,9 +67,9 @@ entry:
 define dso_local void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_ileui_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileus.ll b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
@@ -12,8 +12,8 @@
 define dso_local signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ileus:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -67,9 +67,9 @@ entry:
 define dso_local void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ileus_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -12,8 +12,8 @@
 define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llgeuc:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -64,9 +64,9 @@ entry:
 define dso_local void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llgeuc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -12,8 +12,8 @@
 define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llgeui:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -64,9 +64,9 @@ entry:
 define dso_local void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llgeui_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -12,8 +12,8 @@
 define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgeus:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -64,9 +64,9 @@ entry:
 define dso_local void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgeus_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -12,8 +12,8 @@
 define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llleuc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -67,9 +67,9 @@ entry:
 define dso_local void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llleuc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stb r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
@@ -12,8 +12,8 @@
 define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llleui:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -67,9 +67,9 @@ entry:
 define dso_local void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llleui_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    stw r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -12,8 +12,8 @@
 define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llleus:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -67,9 +67,9 @@ entry:
 define dso_local void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llleus_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    not r4, r4
-; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    addis r4, r2, glob@toc@ha
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    sth r3, glob@toc@l(r4)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/X86/pr31045.ll b/llvm/test/CodeGen/X86/pr31045.ll
@@ -21,11 +21,11 @@ define void @_Z1av() local_unnamed_addr #0 {
 ; CHECK-NEXT:    movl struct_obj_3+8(%rip), %eax
 ; CHECK-NEXT:    movzbl var_46(%rip), %ecx
 ; CHECK-NEXT:    movzbl var_49(%rip), %edx
-; CHECK-NEXT:    addl %ecx, %edx
-; CHECK-NEXT:    notl %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    addl %eax, %eax
-; CHECK-NEXT:    orl $253, %eax
-; CHECK-NEXT:    addl %edx, %eax
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    subl %edx, %eax
+; CHECK-NEXT:    notl %eax
 ; CHECK-NEXT:    movzbl %al, %eax
 ; CHECK-NEXT:    movw %ax, struct_obj_12+5(%rip)
 ; CHECK-NEXT:    movb $0, var_163(%rip)
diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll
@@ -896,11 +896,11 @@ define i64 @opaque_constant(i1 %cond, i64 %x) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    andl $1, %eax
-; X86-NEXT:    negl %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    andl $1, %edx
-; X86-NEXT:    notl %eax
+; X86-NEXT:    negl %edx
+; X86-NEXT:    andl $1, %edx
+; X86-NEXT:    decl %eax
 ; X86-NEXT:    andl $1, %eax
 ; X86-NEXT:    xorl $1, %esi
 ; X86-NEXT:    xorl $1, %ecx
diff --git a/llvm/test/CodeGen/X86/shift-i128.ll b/llvm/test/CodeGen/X86/shift-i128.ll
diff --git a/llvm/test/CodeGen/X86/xor-not-combine.ll b/llvm/test/CodeGen/X86/xor-not-combine.ll
