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1 | | -//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===// |
2 | | -// |
3 | | -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | -// See https://llvm.org/LICENSE.txt for license information. |
5 | | -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | -// |
7 | | -//===----------------------------------------------------------------------===// |
8 | | -// |
9 | | -// This file describes the vendor extensions defined by QUALCOMM. |
10 | | -// |
11 | | -//===----------------------------------------------------------------------===// |
12 | | - |
13 | | -//===----------------------------------------------------------------------===// |
14 | | -// Operand and SDNode transformation definitions. |
15 | | -//===----------------------------------------------------------------------===// |
16 | | - |
17 | | -//===----------------------------------------------------------------------===// |
18 | | -// Instruction Formats |
19 | | -//===----------------------------------------------------------------------===// |
20 | | - |
21 | | -//===----------------------------------------------------------------------===// |
22 | | -// Instruction Class Templates |
23 | | -//===----------------------------------------------------------------------===// |
24 | | - |
25 | | -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { |
26 | | -class QCILoad_ScaleIdx<bits<4> func4, string opcodestr> |
27 | | - : RVInstRBase<0b111, OPC_CUSTOM_0, |
28 | | - (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt), |
29 | | - opcodestr, "$rd, $rs1, $rs2, $shamt"> { |
30 | | - bits<3> shamt; |
31 | | - let Inst{31-28} = func4; |
32 | | - let Inst{27-25} = shamt; |
33 | | -} |
34 | | -} |
35 | | - |
36 | | -let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { |
37 | | -// rd corresponds to the source for the store 'rs3' described in the spec. |
38 | | -class QCIStore_ScaleIdx<bits<4> func4, string opcodestr> |
39 | | - : RVInstRBase<0b110, OPC_CUSTOM_1, (outs), |
40 | | - (ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt), |
41 | | - opcodestr, "$rd, $rs1, $rs2, $shamt"> { |
42 | | - bits<3> shamt; |
43 | | - let Inst{31-28} = func4; |
44 | | - let Inst{27-25} = shamt; |
45 | | -} |
46 | | -} |
47 | | - |
48 | | -//===----------------------------------------------------------------------===// |
49 | | -// Instructions |
50 | | -//===----------------------------------------------------------------------===// |
51 | | - |
52 | | -let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in { |
53 | | -let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { |
54 | | - def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd), |
55 | | - (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr", |
56 | | - "$rd, $rs1, $rs2">; |
57 | | - |
58 | | - def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd), |
59 | | - (ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri", |
60 | | - "$rd, $rs1, $rs2">; |
61 | | -} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 |
62 | | -} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" |
63 | | - |
64 | | -let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in { |
65 | | - def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">; |
66 | | - def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">; |
67 | | - def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">; |
68 | | - def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">; |
69 | | - def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">; |
70 | | - |
71 | | - def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">; |
72 | | - def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">; |
73 | | - def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">; |
74 | | -} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" |
| 1 | +//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +// |
| 9 | +// This file describes the vendor extensions defined by QUALCOMM. |
| 10 | +// |
| 11 | +//===----------------------------------------------------------------------===// |
| 12 | + |
| 13 | +//===----------------------------------------------------------------------===// |
| 14 | +// Operand and SDNode transformation definitions. |
| 15 | +//===----------------------------------------------------------------------===// |
| 16 | + |
| 17 | +def uimm11 : RISCVUImmLeafOp<11>; |
| 18 | + |
| 19 | +//===----------------------------------------------------------------------===// |
| 20 | +// Instruction Formats |
| 21 | +//===----------------------------------------------------------------------===// |
| 22 | + |
| 23 | +//===----------------------------------------------------------------------===// |
| 24 | +// Instruction Class Templates |
| 25 | +//===----------------------------------------------------------------------===// |
| 26 | + |
| 27 | +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { |
| 28 | +class QCILoad_ScaleIdx<bits<4> func4, string opcodestr> |
| 29 | + : RVInstRBase<0b111, OPC_CUSTOM_0, |
| 30 | + (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt), |
| 31 | + opcodestr, "$rd, $rs1, $rs2, $shamt"> { |
| 32 | + bits<3> shamt; |
| 33 | + let Inst{31-28} = func4; |
| 34 | + let Inst{27-25} = shamt; |
| 35 | +} |
| 36 | +} |
| 37 | + |
| 38 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { |
| 39 | +// rd corresponds to the source for the store 'rs3' described in the spec. |
| 40 | +class QCIStore_ScaleIdx<bits<4> func4, string opcodestr> |
| 41 | + : RVInstRBase<0b110, OPC_CUSTOM_1, (outs), |
| 42 | + (ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt), |
| 43 | + opcodestr, "$rd, $rs1, $rs2, $shamt"> { |
| 44 | + bits<3> shamt; |
| 45 | + let Inst{31-28} = func4; |
| 46 | + let Inst{27-25} = shamt; |
| 47 | +} |
| 48 | +} |
| 49 | + |
| 50 | +class QCIRVInstR<bits<4> func4, string opcodestr> |
| 51 | + : RVInstR<{0b000, func4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), |
| 52 | + (ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1"> { |
| 53 | + let rs2 = 0; |
| 54 | +} |
| 55 | + |
| 56 | +class QCIRVInstRR<bits<5> func5, DAGOperand InTyRs1, string opcodestr> |
| 57 | + : RVInstR<{0b00, func5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), |
| 58 | + (ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">; |
| 59 | + |
| 60 | +//===----------------------------------------------------------------------===// |
| 61 | +// Instructions |
| 62 | +//===----------------------------------------------------------------------===// |
| 63 | + |
| 64 | +let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in { |
| 65 | +let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { |
| 66 | + def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd), |
| 67 | + (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr", |
| 68 | + "$rd, $rs1, $rs2">; |
| 69 | + |
| 70 | + def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd), |
| 71 | + (ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri", |
| 72 | + "$rd, $rs1, $rs2">; |
| 73 | +} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 |
| 74 | +} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" |
| 75 | + |
| 76 | +let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in { |
| 77 | + def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">; |
| 78 | + def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">; |
| 79 | + def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">; |
| 80 | + def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">; |
| 81 | + def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">; |
| 82 | + |
| 83 | + def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">; |
| 84 | + def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">; |
| 85 | + def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">; |
| 86 | +} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" |
| 87 | + |
| 88 | +let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in { |
| 89 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { |
| 90 | + def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">; |
| 91 | + def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">; |
| 92 | + def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">; |
| 93 | + def QC_ADDUSAT : QCIRVInstRR<0b01111, GPRNoX0, "qc.addusat">; |
| 94 | + def QC_SUBSAT : QCIRVInstRR<0b10000, GPRNoX0, "qc.subsat">; |
| 95 | + def QC_SUBUSAT : QCIRVInstRR<0b10001, GPRNoX0, "qc.subusat">; |
| 96 | + |
| 97 | + def QC_WRAP : QCIRVInstRR<0b10010, GPR, "qc.wrap">; |
| 98 | + def QC_WRAPI : RVInstI<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd), |
| 99 | + (ins GPRNoX0:$rs1, uimm11:$imm11), "qc.wrapi", |
| 100 | + "$rd, $rs1, $imm11"> { |
| 101 | + bits<11> imm11; |
| 102 | + |
| 103 | + let imm12 = {0b0, imm11}; |
| 104 | + } |
| 105 | + |
| 106 | + def QC_NORM : QCIRVInstR<0b0111, "qc.norm">; |
| 107 | + def QC_NORMU : QCIRVInstR<0b1000, "qc.normu">; |
| 108 | + def QC_NORMEU : QCIRVInstR<0b1001, "qc.normeu">; |
| 109 | +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 |
| 110 | +} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" |
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