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[ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp (#112507)
Fix gcc warnings like: ARMAsmParser.cpp:7168:46: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
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2 files changed

+21
-15
lines changed

2 files changed

+21
-15
lines changed

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2532,14 +2532,14 @@ class ARMOperand : public MCParsedAsmOperand {
25322532
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
25332533
assert(N == 2 && "Invalid number of operands!");
25342534
Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2535-
unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2535+
unsigned RegNum = getCondCode() == ARMCC::AL ? ARM::NoRegister : ARM::CPSR;
25362536
Inst.addOperand(MCOperand::createReg(RegNum));
25372537
}
25382538

25392539
void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
25402540
assert(N == 3 && "Invalid number of operands!");
25412541
Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2542-
unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2542+
unsigned RegNum = getVPTPred() == ARMVCC::None ? ARM::NoRegister : ARM::P0;
25432543
Inst.addOperand(MCOperand::createReg(RegNum));
25442544
Inst.addOperand(MCOperand::createReg(0));
25452545
}
@@ -7164,8 +7164,8 @@ bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
71647164
// Add the carry setting operand, if necessary.
71657165
if (CanAcceptCarrySet && CarrySetting) {
71667166
SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
7167-
Operands.push_back(
7168-
ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, Loc, *this));
7167+
Operands.push_back(ARMOperand::CreateCCOut(
7168+
CarrySetting ? ARM::CPSR : ARM::NoRegister, Loc, *this));
71697169
}
71707170

71717171
// Add the predication code operand, if necessary.
@@ -10372,7 +10372,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1037210372
case ARM::t2ASRri:
1037310373
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
1037410374
isARMLowRegister(Inst.getOperand(1).getReg()) &&
10375-
Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10375+
Inst.getOperand(5).getReg() ==
10376+
(inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
1037610377
!HasWideQualifier) {
1037710378
unsigned NewOpc;
1037810379
switch (Inst.getOpcode()) {
@@ -10422,14 +10423,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1042210423
TmpInst.addOperand(Inst.getOperand(0)); // Rd
1042310424
if (isNarrow)
1042410425
TmpInst.addOperand(MCOperand::createReg(
10425-
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
10426+
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : ARM::NoRegister));
1042610427
TmpInst.addOperand(Inst.getOperand(1)); // Rn
1042710428
TmpInst.addOperand(Inst.getOperand(2)); // Rm
1042810429
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
1042910430
TmpInst.addOperand(Inst.getOperand(5));
1043010431
if (!isNarrow)
1043110432
TmpInst.addOperand(MCOperand::createReg(
10432-
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
10433+
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : ARM::NoRegister));
1043310434
Inst = TmpInst;
1043410435
return true;
1043510436
}
@@ -10475,15 +10476,15 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1047510476
TmpInst.addOperand(Inst.getOperand(0)); // Rd
1047610477
if (isNarrow && !isMov)
1047710478
TmpInst.addOperand(MCOperand::createReg(
10478-
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
10479+
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : ARM::NoRegister));
1047910480
TmpInst.addOperand(Inst.getOperand(1)); // Rn
1048010481
if (newOpc != ARM::t2RRX && !isMov)
1048110482
TmpInst.addOperand(MCOperand::createImm(Amount));
1048210483
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
1048310484
TmpInst.addOperand(Inst.getOperand(4));
1048410485
if (!isNarrow)
1048510486
TmpInst.addOperand(MCOperand::createReg(
10486-
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
10487+
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : ARM::NoRegister));
1048710488
Inst = TmpInst;
1048810489
return true;
1048910490
}
@@ -10684,7 +10685,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1068410685
!isARMLowRegister(Inst.getOperand(0).getReg()) ||
1068510686
(Inst.getOperand(2).isImm() &&
1068610687
(unsigned)Inst.getOperand(2).getImm() > 255) ||
10687-
Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
10688+
Inst.getOperand(5).getReg() !=
10689+
(inITBlock() ? ARM::NoRegister : ARM::CPSR) ||
1068810690
HasWideQualifier)
1068910691
break;
1069010692
MCInst TmpInst;
@@ -10852,7 +10854,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1085210854
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
1085310855
(Inst.getOperand(1).isImm() &&
1085410856
(unsigned)Inst.getOperand(1).getImm() <= 255) &&
10855-
Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10857+
Inst.getOperand(4).getReg() ==
10858+
(inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
1085610859
!HasWideQualifier) {
1085710860
// The operands aren't in the same order for tMOVi8...
1085810861
MCInst TmpInst;
@@ -10993,7 +10996,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1099310996
if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
1099410997
isARMLowRegister(Inst.getOperand(2).getReg())) &&
1099510998
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10996-
Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10999+
Inst.getOperand(5).getReg() ==
11000+
(inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
1099711001
!HasWideQualifier) {
1099811002
unsigned NewOpc;
1099911003
switch (Inst.getOpcode()) {
@@ -11029,7 +11033,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1102911033
isARMLowRegister(Inst.getOperand(2).getReg())) &&
1103011034
(Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
1103111035
Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
11032-
Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
11036+
Inst.getOperand(5).getReg() ==
11037+
(inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
1103311038
!HasWideQualifier) {
1103411039
unsigned NewOpc;
1103511040
switch (Inst.getOpcode()) {

‎llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -894,12 +894,13 @@ void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
894894
MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
895895
if (i > 0 && MCID.operands()[i - 1].isPredicate())
896896
continue;
897-
MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
897+
MI.insert(I,
898+
MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
898899
return;
899900
}
900901
}
901902

902-
MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
903+
MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
903904
}
904905

905906
bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {

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