@@ -1357,17 +1357,10 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
13571357 // DsCnt corresponds to LGKMCnt here.
13581358 return (Decoded.DsCnt == 0 );
13591359 }
1360- case AMDGPU::S_WAIT_STORECNT:
1361- case AMDGPU::S_WAIT_STORECNT_DSCNT:
1362- case AMDGPU::S_WAIT_LOADCNT:
1363- case AMDGPU::S_WAIT_LOADCNT_DSCNT:
1364- case AMDGPU::S_WAIT_SAMPLECNT:
1365- case AMDGPU::S_WAIT_BVHCNT:
1366- case AMDGPU::S_WAIT_DSCNT:
1367- case AMDGPU::S_WAIT_EXPCNT:
1368- case AMDGPU::S_WAIT_KMCNT:
1369- llvm_unreachable (" unexpected wait count instruction" );
13701360 default :
1361+ assert ((!SIInstrInfo::isWaitcnt (MI.getOpcode ()) ||
1362+ MI.getOpcode () == AMDGPU::S_WAIT_IDLE) &&
1363+ " unexpected wait count instruction" );
13711364 // SOPP instructions cannot mitigate the hazard.
13721365 if (TII->isSOPP (MI))
13731366 return false ;
@@ -2257,28 +2250,7 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
22572250 if (WaitStates >= 3 || SIInstrInfo::isVALU (MI))
22582251 return true ;
22592252
2260- switch (MI.getOpcode ()) {
2261- case AMDGPU::S_WAITCNT:
2262- case AMDGPU::S_WAITCNT_VSCNT:
2263- case AMDGPU::S_WAITCNT_VMCNT:
2264- case AMDGPU::S_WAITCNT_EXPCNT:
2265- case AMDGPU::S_WAITCNT_LGKMCNT:
2266- case AMDGPU::S_WAIT_IDLE:
2267- case AMDGPU::S_WAIT_LOADCNT:
2268- case AMDGPU::S_WAIT_LOADCNT_DSCNT:
2269- case AMDGPU::S_WAIT_SAMPLECNT:
2270- case AMDGPU::S_WAIT_BVHCNT:
2271- case AMDGPU::S_WAIT_STORECNT:
2272- case AMDGPU::S_WAIT_STORECNT_DSCNT:
2273- case AMDGPU::S_WAIT_EXPCNT:
2274- case AMDGPU::S_WAIT_DSCNT:
2275- case AMDGPU::S_WAIT_KMCNT:
2276- return true ;
2277- default :
2278- break ;
2279- }
2280-
2281- return false ;
2253+ return SIInstrInfo::isWaitcnt (MI.getOpcode ());
22822254 };
22832255
22842256 return FPAtomicToDenormModeWaitStates -
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