Skip to content

Commit f169ea3

Browse files
topperctopperc
committed
[RISCV][GISel] Widen G_ABDS/G_ABDU before lowering when Zbb is enabled.
This allows us to use G_SMIN/SMAX in the lowering.
1 parent 2422686 commit f169ea3

File tree

3 files changed

+109
-53
lines changed

3 files changed

+109
-53
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2916,6 +2916,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
29162916
case TargetOpcode::G_SREM:
29172917
case TargetOpcode::G_SMIN:
29182918
case TargetOpcode::G_SMAX:
2919+
case TargetOpcode::G_ABDS:
29192920
Observer.changingInstr(MI);
29202921
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
29212922
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
@@ -2953,6 +2954,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
29532954
return Legalized;
29542955
case TargetOpcode::G_UDIV:
29552956
case TargetOpcode::G_UREM:
2957+
case TargetOpcode::G_ABDU:
29562958
Observer.changingInstr(MI);
29572959
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
29582960
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -488,7 +488,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
488488
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
489489
.lower();
490490

491-
getActionDefinitionsBuilder({G_ABDS, G_ABDU}).lower();
491+
getActionDefinitionsBuilder({G_ABDS, G_ABDU})
492+
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
493+
.lower();
492494

493495
getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN})
494496
.legalFor(ST.hasStdExtZbb(), {sXLen})

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir‎

Lines changed: 104 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -9,19 +9,32 @@ name: abds_i8
99
body: |
1010
bb.0.entry:
1111
liveins: $x10, $x11
12-
; CHECK-LABEL: name: abds_i8
13-
; CHECK: liveins: $x10, $x11
14-
; CHECK-NEXT: {{ $}}
15-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
16-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
17-
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
18-
; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
19-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
20-
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
21-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
22-
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
23-
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
24-
; CHECK-NEXT: PseudoRET implicit $x10
12+
; RV32I-LABEL: name: abds_i8
13+
; RV32I: liveins: $x10, $x11
14+
; RV32I-NEXT: {{ $}}
15+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
16+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
17+
; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
18+
; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
19+
; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
20+
; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
21+
; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
22+
; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
23+
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
24+
; RV32I-NEXT: PseudoRET implicit $x10
25+
;
26+
; RV32ZBB-LABEL: name: abds_i8
27+
; RV32ZBB: liveins: $x10, $x11
28+
; RV32ZBB-NEXT: {{ $}}
29+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
30+
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
31+
; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
32+
; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
33+
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
34+
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
35+
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
36+
; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
37+
; RV32ZBB-NEXT: PseudoRET implicit $x10
2538
%1:_(s32) = COPY $x10
2639
%2:_(s32) = COPY $x11
2740
%3:_(s32) = G_ASSERT_SEXT %1, 8
@@ -38,19 +51,32 @@ name: abds_i16
3851
body: |
3952
bb.0.entry:
4053
liveins: $x10, $x11
41-
; CHECK-LABEL: name: abds_i16
42-
; CHECK: liveins: $x10, $x11
43-
; CHECK-NEXT: {{ $}}
44-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
45-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
46-
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
47-
; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
48-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
49-
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
50-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
51-
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
52-
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
53-
; CHECK-NEXT: PseudoRET implicit $x10
54+
; RV32I-LABEL: name: abds_i16
55+
; RV32I: liveins: $x10, $x11
56+
; RV32I-NEXT: {{ $}}
57+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
58+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
59+
; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
60+
; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
61+
; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
62+
; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
63+
; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
64+
; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
65+
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
66+
; RV32I-NEXT: PseudoRET implicit $x10
67+
;
68+
; RV32ZBB-LABEL: name: abds_i16
69+
; RV32ZBB: liveins: $x10, $x11
70+
; RV32ZBB-NEXT: {{ $}}
71+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
72+
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
73+
; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
74+
; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
75+
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
76+
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
77+
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
78+
; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
79+
; RV32ZBB-NEXT: PseudoRET implicit $x10
5480
%1:_(s32) = COPY $x10
5581
%2:_(s32) = COPY $x11
5682
%3:_(s32) = G_ASSERT_SEXT %1, 16
@@ -138,19 +164,32 @@ name: abdu_i8
138164
body: |
139165
bb.0.entry:
140166
liveins: $x10, $x11
141-
; CHECK-LABEL: name: abdu_i8
142-
; CHECK: liveins: $x10, $x11
143-
; CHECK-NEXT: {{ $}}
144-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
145-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
146-
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
147-
; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
148-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
149-
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
150-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
151-
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
152-
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
153-
; CHECK-NEXT: PseudoRET implicit $x10
167+
; RV32I-LABEL: name: abdu_i8
168+
; RV32I: liveins: $x10, $x11
169+
; RV32I-NEXT: {{ $}}
170+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
171+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
172+
; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
173+
; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
174+
; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
175+
; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
176+
; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
177+
; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
178+
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
179+
; RV32I-NEXT: PseudoRET implicit $x10
180+
;
181+
; RV32ZBB-LABEL: name: abdu_i8
182+
; RV32ZBB: liveins: $x10, $x11
183+
; RV32ZBB-NEXT: {{ $}}
184+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
185+
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
186+
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
187+
; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
188+
; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
189+
; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
190+
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]
191+
; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
192+
; RV32ZBB-NEXT: PseudoRET implicit $x10
154193
%1:_(s32) = COPY $x10
155194
%2:_(s32) = COPY $x11
156195
%3:_(s32) = G_ASSERT_ZEXT %1, 8
@@ -167,19 +206,32 @@ name: abdu_i16
167206
body: |
168207
bb.0.entry:
169208
liveins: $x10, $x11
170-
; CHECK-LABEL: name: abdu_i16
171-
; CHECK: liveins: $x10, $x11
172-
; CHECK-NEXT: {{ $}}
173-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
174-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
175-
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
176-
; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
177-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
178-
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
179-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
180-
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
181-
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
182-
; CHECK-NEXT: PseudoRET implicit $x10
209+
; RV32I-LABEL: name: abdu_i16
210+
; RV32I: liveins: $x10, $x11
211+
; RV32I-NEXT: {{ $}}
212+
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
213+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
214+
; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
215+
; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
216+
; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
217+
; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
218+
; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
219+
; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
220+
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
221+
; RV32I-NEXT: PseudoRET implicit $x10
222+
;
223+
; RV32ZBB-LABEL: name: abdu_i16
224+
; RV32ZBB: liveins: $x10, $x11
225+
; RV32ZBB-NEXT: {{ $}}
226+
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
227+
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
228+
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
229+
; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
230+
; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
231+
; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
232+
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]
233+
; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
234+
; RV32ZBB-NEXT: PseudoRET implicit $x10
183235
%1:_(s32) = COPY $x10
184236
%2:_(s32) = COPY $x11
185237
%3:_(s32) = G_ASSERT_ZEXT %1, 16

0 commit comments

Comments
 (0)