update test

Author: el-ev

llvm/test/Transforms/InstCombine/ceil-shift.ll

@@ -4,12 +4,7 @@
 define i1 @ceil_shift4(i32 %arg0) {
 ; CHECK-LABEL: define i1 @ceil_shift4(
 ; CHECK-SAME: i32 [[ARG0:%.*]]) {
-; CHECK-NEXT:    [[TMP6:%.*]] = lshr i32 [[ARG0]], 4
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[ARG0]], 15
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
-; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = lshr i32 %arg0, 4
@@ -24,12 +19,7 @@ define i1 @ceil_shift4(i32 %arg0) {
 define i1 @ceil_shift6(i32 %arg0) {
 ; CHECK-LABEL: define i1 @ceil_shift6(
 ; CHECK-SAME: i32 [[ARG0:%.*]]) {
-; CHECK-NEXT:    [[TMP6:%.*]] = lshr i32 [[ARG0]], 6
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[ARG0]], 63
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
-; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = lshr i32 %arg0, 6
@@ -44,12 +34,7 @@ define i1 @ceil_shift6(i32 %arg0) {
 define i1 @ceil_shift11(i32 %arg0) {
 ; CHECK-LABEL: define i1 @ceil_shift11(
 ; CHECK-SAME: i32 [[ARG0:%.*]]) {
-; CHECK-NEXT:    [[TMP6:%.*]] = lshr i32 [[ARG0]], 11
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[ARG0]], 2047
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
-; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = lshr i32 %arg0, 11
@@ -83,11 +68,7 @@ define i1 @ceil_shift4_used_1(i32 %arg0) {
 ; CHECK-SAME: i32 [[ARG0:%.*]]) {
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
 ; CHECK-NEXT:    call void @use(i32 [[TMP1]])
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[ARG0]], 15
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
-; CHECK-NEXT:    [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
-; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[ARG0]], 0
 ; CHECK-NEXT:    ret i1 [[TMP6]]
 ;
   %1 = lshr i32 %arg0, 4
@@ -125,12 +106,7 @@ define i1 @ceil_shift4_used_5(i32 %arg0) {
 define <4 x i1> @ceil_shift4_v4i32(<4 x i32> %arg0) {
 ; CHECK-LABEL: define <4 x i1> @ceil_shift4_v4i32(
 ; CHECK-SAME: <4 x i32> [[ARG0:%.*]]) {
-; CHECK-NEXT:    [[TMP6:%.*]] = lshr <4 x i32> [[ARG0]], splat (i32 16)
-; CHECK-NEXT:    [[TMP2:%.*]] = and <4 x i32> [[ARG0]], splat (i32 65535)
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT:    [[TMP4:%.*]] = zext <4 x i1> [[TMP3]] to <4 x i32>
-; CHECK-NEXT:    [[TMP5:%.*]] = or <4 x i32> [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <4 x i32> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <4 x i32> [[ARG0]], zeroinitializer
 ; CHECK-NEXT:    ret <4 x i1> [[TMP1]]
 ;
   %1 = lshr <4 x i32> %arg0, splat (i32 16)
@@ -145,12 +121,7 @@ define <4 x i1> @ceil_shift4_v4i32(<4 x i32> %arg0) {
 define <8 x i1> @ceil_shift4_v8i16(<8 x i16> %arg0) {
 ; CHECK-LABEL: define <8 x i1> @ceil_shift4_v8i16(
 ; CHECK-SAME: <8 x i16> [[ARG0:%.*]]) {
-; CHECK-NEXT:    [[TMP6:%.*]] = lshr <8 x i16> [[ARG0]], splat (i16 4)
-; CHECK-NEXT:    [[TMP2:%.*]] = and <8 x i16> [[ARG0]], splat (i16 15)
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer
-; CHECK-NEXT:    [[TMP4:%.*]] = zext <8 x i1> [[TMP3]] to <8 x i16>
-; CHECK-NEXT:    [[TMP5:%.*]] = or <8 x i16> [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> [[ARG0]], zeroinitializer
 ; CHECK-NEXT:    ret <8 x i1> [[TMP1]]
 ;
   %1 = lshr <8 x i16> %arg0, splat (i16 4)