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[VPlan] Use VPIRMetadata for VPInterleaveRecipe.
Use VPIRMetadata for VPInterleaveRecipe to preserve noalias metadata added by versioning. This still uses InterleaveGroup's logic to preserve existing metadata from IR. This can be migrated separately. Fixes #153006.
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6 files changed

+70
-57
lines changed

6 files changed

+70
-57
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.h‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -943,6 +943,10 @@ class VPIRMetadata {
943943
void addMetadata(unsigned Kind, MDNode *Node) {
944944
Metadata.emplace_back(Kind, Node);
945945
}
946+
947+
/// Intersect the this VPIRMetada objet with \p MD, keeping only metadata
948+
/// nodes in both.
949+
void intersect(const VPIRMetadata &MD);
946950
};
947951

948952
/// This is a concrete Recipe that models a single VPlan-level instruction.
@@ -2426,7 +2430,8 @@ class LLVM_ABI_FOR_TEST VPBlendRecipe : public VPSingleDefRecipe {
24262430
/// or stores into one wide load/store and shuffles. The first operand of a
24272431
/// VPInterleave recipe is the address, followed by the stored values, followed
24282432
/// by an optional mask.
2429-
class LLVM_ABI_FOR_TEST VPInterleaveRecipe : public VPRecipeBase {
2433+
class LLVM_ABI_FOR_TEST VPInterleaveRecipe : public VPRecipeBase,
2434+
public VPIRMetadata {
24302435
const InterleaveGroup<Instruction> *IG;
24312436

24322437
/// Indicates if the interleave group is in a conditional block and requires a
@@ -2440,10 +2445,8 @@ class LLVM_ABI_FOR_TEST VPInterleaveRecipe : public VPRecipeBase {
24402445
public:
24412446
VPInterleaveRecipe(const InterleaveGroup<Instruction> *IG, VPValue *Addr,
24422447
ArrayRef<VPValue *> StoredValues, VPValue *Mask,
2443-
bool NeedsMaskForGaps, DebugLoc DL)
2444-
: VPRecipeBase(VPDef::VPInterleaveSC, {Addr},
2445-
DL),
2446-
2448+
bool NeedsMaskForGaps, const VPIRMetadata &MD, DebugLoc DL)
2449+
: VPRecipeBase(VPDef::VPInterleaveSC, {Addr}, DL), VPIRMetadata(MD),
24472450
IG(IG), NeedsMaskForGaps(NeedsMaskForGaps) {
24482451
// TODO: extend the masked interleaved-group support to reversed access.
24492452
assert((!Mask || !IG->isReverse()) &&
@@ -2466,7 +2469,7 @@ class LLVM_ABI_FOR_TEST VPInterleaveRecipe : public VPRecipeBase {
24662469

24672470
VPInterleaveRecipe *clone() override {
24682471
return new VPInterleaveRecipe(IG, getAddr(), getStoredValues(), getMask(),
2469-
NeedsMaskForGaps, getDebugLoc());
2472+
NeedsMaskForGaps, *this, getDebugLoc());
24702473
}
24712474

24722475
VP_CLASSOF_IMPL(VPDef::VPInterleaveSC)

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1560,6 +1560,17 @@ void VPIRMetadata::applyMetadata(Instruction &I) const {
15601560
I.setMetadata(Kind, Node);
15611561
}
15621562

1563+
void VPIRMetadata::intersect(const VPIRMetadata &Other) {
1564+
SmallVector<std::pair<unsigned, MDNode *>> MetadataUnion;
1565+
for (const auto &[KindA, MDA] : Metadata) {
1566+
for (const auto &[KindB, MDB] : Other.Metadata) {
1567+
if (KindA == KindB && MDA == MDB)
1568+
MetadataUnion.emplace_back(KindA, MDA);
1569+
}
1570+
}
1571+
Metadata = std::move(MetadataUnion);
1572+
}
1573+
15631574
void VPWidenCallRecipe::execute(VPTransformState &State) {
15641575
assert(State.VF.isVector() && "not widening");
15651576
assert(Variant != nullptr && "Can't create vector function.");
@@ -3575,6 +3586,8 @@ void VPInterleaveRecipe::execute(VPTransformState &State) {
35753586
} else
35763587
NewLoad = State.Builder.CreateAlignedLoad(VecTy, ResAddr,
35773588
Group->getAlign(), "wide.vec");
3589+
applyMetadata(*NewLoad);
3590+
// TODO: Also manage existing metadata using VPIRMetadata.
35783591
Group->addMetadata(NewLoad);
35793592

35803593
ArrayRef<VPValue *> VPDefs = definedValues();
@@ -3677,6 +3690,8 @@ void VPInterleaveRecipe::execute(VPTransformState &State) {
36773690
NewStoreInstr =
36783691
State.Builder.CreateAlignedStore(IVec, ResAddr, Group->getAlign());
36793692

3693+
applyMetadata(*NewStoreInstr);
3694+
// TODO: Also manage existing metadata using VPIRMetadata.
36803695
Group->addMetadata(NewStoreInstr);
36813696
}
36823697

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 19 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2612,12 +2612,24 @@ void VPlanTransforms::createInterleaveGroups(
26122612
VPDominatorTree VPDT;
26132613
VPDT.recalculate(Plan);
26142614
for (const auto *IG : InterleaveGroups) {
2615+
// Get or create the start address for the interleave group.
2616+
auto *Start =
2617+
cast<VPWidenMemoryRecipe>(RecipeBuilder.getRecipe(IG->getMember(0)));
2618+
2619+
VPIRMetadata InterleaveMD(*Start);
26152620
SmallVector<VPValue *, 4> StoredValues;
2616-
for (unsigned i = 0; i < IG->getFactor(); ++i)
2617-
if (auto *SI = dyn_cast_or_null<StoreInst>(IG->getMember(i))) {
2618-
auto *StoreR = cast<VPWidenStoreRecipe>(RecipeBuilder.getRecipe(SI));
2621+
for (unsigned i = 0; i < IG->getFactor(); ++i) {
2622+
Instruction *MemI = IG->getMember(i);
2623+
if (!MemI)
2624+
continue;
2625+
VPWidenMemoryRecipe *MemR =
2626+
cast<VPWidenMemoryRecipe>(RecipeBuilder.getRecipe(MemI));
2627+
if (!MemR)
2628+
continue;
2629+
if (auto *StoreR = dyn_cast<VPWidenStoreRecipe>(MemR))
26192630
StoredValues.push_back(StoreR->getStoredValue());
2620-
}
2631+
InterleaveMD.intersect(*MemR);
2632+
}
26212633

26222634
bool NeedsMaskForGaps =
26232635
(IG->requiresScalarEpilogue() && !ScalarEpilogueAllowed) ||
@@ -2632,9 +2644,6 @@ void VPlanTransforms::createInterleaveGroups(
26322644
getLoadStorePointerOperand(IRInsertPos)->stripPointerCasts()))
26332645
NW = Gep->getNoWrapFlags().withoutNoUnsignedWrap();
26342646

2635-
// Get or create the start address for the interleave group.
2636-
auto *Start =
2637-
cast<VPWidenMemoryRecipe>(RecipeBuilder.getRecipe(IG->getMember(0)));
26382647
VPValue *Addr = Start->getAddr();
26392648
VPRecipeBase *AddrDef = Addr->getDefiningRecipe();
26402649
if (AddrDef && !VPDT.properlyDominates(AddrDef, InsertPos)) {
@@ -2667,8 +2676,10 @@ void VPlanTransforms::createInterleaveGroups(
26672676
ReversePtr->insertBefore(InsertPos);
26682677
Addr = ReversePtr;
26692678
}
2679+
26702680
auto *VPIG = new VPInterleaveRecipe(IG, Addr, StoredValues,
2671-
InsertPos->getMask(), NeedsMaskForGaps, InsertPos->getDebugLoc());
2681+
InsertPos->getMask(), NeedsMaskForGaps,
2682+
InterleaveMD, InsertPos->getDebugLoc());
26722683
VPIG->insertBefore(InsertPos);
26732684

26742685
unsigned J = 0;

‎llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll‎

Lines changed: 9 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ define void @geps_feeding_interleave_groups_with_reuse(ptr %arg, i64 %arg1, ptr
145145
; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 [[TMP9]]
146146
; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[INDEX]], 4
147147
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[ARG2]], i64 [[TMP11]]
148-
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x float>, ptr [[TMP26]], align 4
148+
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x float>, ptr [[TMP26]], align 4, !alias.scope [[META4:![0-9]+]]
149149
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 0, i32 8>
150150
; CHECK-NEXT: [[STRIDED_VEC14:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 1, i32 9>
151151
; CHECK-NEXT: [[STRIDED_VEC15:%.*]] = shufflevector <16 x float> [[WIDE_VEC]], <16 x float> poison, <2 x i32> <i32 2, i32 10>
@@ -166,10 +166,10 @@ define void @geps_feeding_interleave_groups_with_reuse(ptr %arg, i64 %arg1, ptr
166166
; CHECK-NEXT: [[TMP41:%.*]] = shufflevector <2 x float> [[TMP35]], <2 x float> [[TMP37]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
167167
; CHECK-NEXT: [[TMP42:%.*]] = shufflevector <4 x float> [[TMP40]], <4 x float> [[TMP41]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
168168
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x float> [[TMP42]], <8 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
169-
; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC]], ptr [[TMP28]], align 4
169+
; CHECK-NEXT: store <8 x float> [[INTERLEAVED_VEC]], ptr [[TMP28]], align 4, !alias.scope [[META7:![0-9]+]], !noalias [[META4]]
170170
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
171171
; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
172-
; CHECK-NEXT: br i1 [[TMP43]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
172+
; CHECK-NEXT: br i1 [[TMP43]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
173173
; CHECK: [[MIDDLE_BLOCK]]:
174174
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
175175
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -215,7 +215,7 @@ define void @geps_feeding_interleave_groups_with_reuse(ptr %arg, i64 %arg1, ptr
215215
; CHECK-NEXT: store float [[MUL_4]], ptr [[GEP_11]], align 4
216216
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
217217
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[ARG1]]
218-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
218+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
219219
; CHECK: [[EXIT]]:
220220
; CHECK-NEXT: ret void
221221
;
@@ -396,24 +396,24 @@ define void @geps_feeding_interleave_groups_with_reuse2(ptr %A, ptr %B, i64 %N)
396396
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8
397397
; CHECK-NEXT: [[TMP51:%.*]] = lshr exact i64 [[OFFSET_IDX]], 1
398398
; CHECK-NEXT: [[TMP52:%.*]] = getelementptr nusw i32, ptr [[B]], i64 [[TMP51]]
399-
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP52]], align 4
399+
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP52]], align 4, !alias.scope [[META11:![0-9]+]], !noalias [[META14:![0-9]+]]
400400
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
401401
; CHECK-NEXT: [[STRIDED_VEC34:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
402402
; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr [[A]], i64 [[OFFSET_IDX]]
403403
; CHECK-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[B]], <4 x i64> [[VEC_IND]]
404-
; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> [[TMP54]], i32 4, <4 x i1> splat (i1 true), <4 x i32> poison), !alias.scope [[META6:![0-9]+]], !noalias [[META9:![0-9]+]]
404+
; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> [[TMP54]], i32 4, <4 x i1> splat (i1 true), <4 x i32> poison), !alias.scope [[META16:![0-9]+]], !noalias [[META14]]
405405
; CHECK-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[STRIDED_VEC]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
406406
; CHECK-NEXT: [[TMP59:%.*]] = shufflevector <4 x i32> [[STRIDED_VEC34]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
407407
; CHECK-NEXT: [[TMP60:%.*]] = shufflevector <4 x i32> [[WIDE_MASKED_GATHER]], <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
408408
; CHECK-NEXT: [[TMP61:%.*]] = shufflevector <8 x i32> [[TMP58]], <8 x i32> [[TMP59]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
409409
; CHECK-NEXT: [[TMP62:%.*]] = shufflevector <8 x i32> [[TMP60]], <8 x i32> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
410410
; CHECK-NEXT: [[TMP63:%.*]] = shufflevector <16 x i32> [[TMP61]], <16 x i32> [[TMP62]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
411411
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <32 x i32> [[TMP63]], <32 x i32> poison, <32 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
412-
; CHECK-NEXT: store <32 x i32> [[INTERLEAVED_VEC]], ptr [[TMP56]], align 4
412+
; CHECK-NEXT: store <32 x i32> [[INTERLEAVED_VEC]], ptr [[TMP56]], align 4, !alias.scope [[META14]]
413413
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
414414
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 32)
415415
; CHECK-NEXT: [[TMP64:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
416-
; CHECK-NEXT: br i1 [[TMP64]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
416+
; CHECK-NEXT: br i1 [[TMP64]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
417417
; CHECK: [[MIDDLE_BLOCK]]:
418418
; CHECK-NEXT: br label %[[SCALAR_PH]]
419419
; CHECK: [[SCALAR_PH]]:
@@ -454,7 +454,7 @@ define void @geps_feeding_interleave_groups_with_reuse2(ptr %A, ptr %B, i64 %N)
454454
; CHECK-NEXT: store i32 0, ptr [[GEP_A_7]], align 4
455455
; CHECK-NEXT: [[IV_NEXT_7]] = add nuw nsw i64 [[IV]], 8
456456
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
457-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
457+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]
458458
; CHECK: [[EXIT]]:
459459
; CHECK-NEXT: ret void
460460
;
@@ -511,8 +511,6 @@ define void @interleave_store_double_i64(ptr %dst) {
511511
; CHECK: [[VECTOR_PH]]:
512512
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
513513
; CHECK: [[VECTOR_BODY]]:
514-
; CHECK-NEXT: store <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 4.940660e-324>, ptr [[DST]], align 8
515-
; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]
516514
; CHECK: [[MIDDLE_BLOCK]]:
517515
; CHECK-NEXT: br label %[[EXIT:.*]]
518516
; CHECK: [[SCALAR_PH]]:
@@ -525,7 +523,6 @@ define void @interleave_store_double_i64(ptr %dst) {
525523
; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_0]], align 8
526524
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
527525
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
528-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
529526
; CHECK: [[EXIT]]:
530527
; CHECK-NEXT: ret void
531528
;
@@ -623,8 +620,6 @@ define void @interleave_store_i64_double_2(ptr %dst) {
623620
; CHECK: [[VECTOR_PH]]:
624621
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
625622
; CHECK: [[VECTOR_BODY]]:
626-
; CHECK-NEXT: store <4 x double> <double 0.000000e+00, double 0.000000e+00, double 4.940660e-324, double 0.000000e+00>, ptr [[DST]], align 8
627-
; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]
628623
; CHECK: [[MIDDLE_BLOCK]]:
629624
; CHECK-NEXT: br label %[[EXIT:.*]]
630625
; CHECK: [[SCALAR_PH]]:
@@ -637,7 +632,6 @@ define void @interleave_store_i64_double_2(ptr %dst) {
637632
; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_1]], align 8
638633
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
639634
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
640-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
641635
; CHECK: [[EXIT]]:
642636
; CHECK-NEXT: ret void
643637
;
@@ -668,15 +662,3 @@ attributes #1 = { "min-legal-vector-width"="0" "target-cpu"="cascadelake" }
668662
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
669663
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
670664
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
671-
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
672-
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
673-
; CHECK: [[META6]] = !{[[META7:![0-9]+]]}
674-
; CHECK: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]}
675-
; CHECK: [[META8]] = distinct !{[[META8]], !"LVerDomain"}
676-
; CHECK: [[META9]] = !{[[META10:![0-9]+]]}
677-
; CHECK: [[META10]] = distinct !{[[META10]], [[META8]]}
678-
; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]}
679-
; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]]}
680-
; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]}
681-
; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META2]], [[META1]]}
682-
;.

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