Add signext to cases

Author: ecnelises

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -14563,9 +14563,7 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const {
     };
     // ult (add x -0x80000000) -0x100000000 -> ne x (sext:i64 (trunc:i32 x))
     // ult (add x -0x8000) -0x10000 -> ne x (sext:i64 (trunc:i16 x))
-    // ult (add x -0x80) -0x100 -> ne x (sext:i64 (trunc:i8 x))
-    // ult (add x -0x80) -0x100 -> ne x (sext:i32 (trunc:i16 x))
-    // ult (add x -0x80) -0x100 -> ne x (sext:i16 (trunc:i8 x))
+    // ult (add x -0x80) -0x100 -> ne x (sext:i64/i32/i16 (trunc:i8/i16/i8 x))
     if (LHS.getOpcode() == ISD::ADD) {
       const auto *Addend = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
       const auto *RhsC = dyn_cast<ConstantSDNode>(RHS);

llvm/test/CodeGen/PowerPC/setcc-to-sub.ll

@@ -131,7 +131,7 @@ entry:
   ret i1 %cmp
 }
 
-define zeroext i1 @test8(i32 %a) {
+define zeroext i1 @test8(i32 signext %a) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb 4, 3
@@ -146,7 +146,7 @@ entry:
   ret i1 %cmp
 }
 
-define zeroext i1 @test9(i32 %a) {
+define zeroext i1 @test9(i32 signext %a) {
 ; CHECK-LABEL: test9:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    extsb 4, 3
@@ -161,13 +161,11 @@ entry:
   ret i1 %cmp
 }
 
-define zeroext i1 @test10(i16 %a) {
+define zeroext i1 @test10(i16 signext %a) {
 ; CHECK-LABEL: test10:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrlwi 4, 3, 16
-; CHECK-NEXT:    extsb 3, 3
-; CHECK-NEXT:    clrlwi 3, 3, 16
-; CHECK-NEXT:    xor 3, 4, 3
+; CHECK-NEXT:    extsb 4, 3
+; CHECK-NEXT:    xor 3, 3, 4
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 5
 ; CHECK-NEXT:    xori 3, 3, 1