Merge branch 'main' into hgh/libcxx/P2255R2-A_type_trait_to_detect_reference_binding_to_temporary

Author: H-G-Hristov

compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc

@@ -3205,6 +3205,28 @@ POST_SYSCALL(futex)
   COMMON_SYSCALL_BLOCKING_END();
 }
 
+PRE_SYSCALL(copy_file_range)
+(int fdin, __sanitizer___kernel_off_t *offin, int fdout,
+ __sanitizer___kernel_off_t *offout, SIZE_T size, unsigned int flags) {
+  if (offin != nullptr) {
+    PRE_READ(offin, sizeof(*offin));
+  }
+  if (offout != nullptr) {
+    PRE_READ(offout, sizeof(*offout));
+  }
+}
+
+POST_SYSCALL(copy_file_range)
+(SSIZE_T, int fdin, __sanitizer___kernel_off_t *offin, int fdout,
+ __sanitizer___kernel_off_t *offout, SIZE_T size, unsigned int flags) {
+  if (offin != nullptr) {
+    POST_WRITE(offin, sizeof(*offin));
+  }
+  if (offout != nullptr) {
+    POST_WRITE(offout, sizeof(*offout));
+  }
+}
+
 }  // extern "C"
 
 #  undef PRE_SYSCALL

compiler-rt/test/sanitizer_common/TestCases/Linux/copy_file_range.c

@@ -0,0 +1,42 @@
+// RUN: %clangxx -O0 %s -D_FILE_OFFSET_BITS=64 -o %t
+
+// REQUIRES: glibc
+
+#ifndef _GNU_SOURCE
+#  define _GNU_SOURCE
+#endif
+#include <assert.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <sys/syscall.h>
+#include <unistd.h>
+
+#if !defined(__GLIBC_PREREQ)
+#  define __GLIBC_PREREQ(a, b) 0
+#endif
+
+#if !__GLIBC_PREREQ(2, 27)
+#  define copy_file_range(a, b, c, d, e)                                       \
+    (ssize_t) syscall(__NR_copy_file_range, a, b, c, d, e)
+#endif
+
+int main(void) {
+  int fdin = open("/proc/self/maps", O_RDONLY);
+  assert(fdin > 0);
+  char tmp[] = "/tmp/map.XXXXXX";
+  int fdout = mkstemp(tmp);
+  assert(fdout > 0);
+  off_t offin = -1, offout = 0;
+  ssize_t cpy = copy_file_range(fdin, &offin, fdout, &offout, 8, 0);
+  assert(cpy < 0);
+  offin = 0;
+  offout = 16;
+  cpy = copy_file_range(fdin, &offin, fdout, &offout, 8, 0);
+  assert(cpy < 0);
+  offout = 0;
+  cpy = copy_file_range(fdin, &offin, fdout, &offout, 8, 0);
+  assert(cpy == 8);
+  close(fdout);
+  close(fdin);
+  return 0;
+}

llvm/include/llvm/ADT/APFloat.h

@@ -1543,11 +1543,16 @@ inline APFloat neg(APFloat X) {
   return X;
 }
 
-/// Implements IEEE-754 2019 minimumNumber semantics. Returns the smaller of the
-/// 2 arguments if both are not NaN. If either argument is a NaN, returns the
-/// other argument. -0 is treated as ordered less than +0.
+/// Implements IEEE-754 2008 minNum semantics. Returns the smaller of the
+/// 2 arguments if both are not NaN. If either argument is a qNaN, returns the
+/// other argument. If either argument is sNaN, return a qNaN.
+/// -0 is treated as ordered less than +0.
 LLVM_READONLY
 inline APFloat minnum(const APFloat &A, const APFloat &B) {
+  if (A.isSignaling())
+    return A.makeQuiet();
+  if (B.isSignaling())
+    return B.makeQuiet();
   if (A.isNaN())
     return B;
   if (B.isNaN())
@@ -1557,11 +1562,16 @@ inline APFloat minnum(const APFloat &A, const APFloat &B) {
   return B < A ? B : A;
 }
 
-/// Implements IEEE-754 2019 maximumNumber semantics. Returns the larger of the
-/// 2 arguments if both are not NaN. If either argument is a NaN, returns the
-/// other argument. +0 is treated as ordered greater than -0.
+/// Implements IEEE-754 2008 maxNum semantics. Returns the larger of the
+/// 2 arguments if both are not NaN. If either argument is a qNaN, returns the
+/// other argument. If either argument is sNaN, return a qNaN.
+/// +0 is treated as ordered greater than -0.
 LLVM_READONLY
 inline APFloat maxnum(const APFloat &A, const APFloat &B) {
+  if (A.isSignaling())
+    return A.makeQuiet();
+  if (B.isSignaling())
+    return B.makeQuiet();
   if (A.isNaN())
     return B;
   if (B.isNaN())

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -4920,6 +4920,18 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
       return false;
     }
 
+    for (auto Op : {AMDGPU::OpName::src0_sel, AMDGPU::OpName::src1_sel,
+                    AMDGPU::OpName::dst_sel}) {
+      const MachineOperand *MO = getNamedOperand(MI, Op);
+      if (!MO)
+        continue;
+      int64_t Imm = MO->getImm();
+      if (Imm < 0 || Imm > AMDGPU::SDWA::SdwaSel::DWORD) {
+        ErrInfo = "Invalid SDWA selection";
+        return false;
+      }
+    }
+
     int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
 
     for (int OpIdx : {DstIdx, Src0Idx, Src1Idx, Src2Idx}) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

@@ -186,13 +186,10 @@ void RISCVELFStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
   MCELFStreamer::emitValueImpl(Value, Size, Loc);
 }
 
-namespace llvm {
-MCELFStreamer *createRISCVELFStreamer(MCContext &C,
-                                      std::unique_ptr<MCAsmBackend> MAB,
-                                      std::unique_ptr<MCObjectWriter> MOW,
-                                      std::unique_ptr<MCCodeEmitter> MCE) {
-  RISCVELFStreamer *S =
-      new RISCVELFStreamer(C, std::move(MAB), std::move(MOW), std::move(MCE));
-  return S;
-}
-} // namespace llvm
+MCStreamer *llvm::createRISCVELFStreamer(const Triple &, MCContext &C,
+                                         std::unique_ptr<MCAsmBackend> &&MAB,
+                                         std::unique_ptr<MCObjectWriter> &&MOW,
+                                         std::unique_ptr<MCCodeEmitter> &&MCE) {
+  return new RISCVELFStreamer(C, std::move(MAB), std::move(MOW),
+                              std::move(MCE));
+}

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h

@@ -69,10 +69,10 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
   void finish() override;
 };
 
-MCELFStreamer *createRISCVELFStreamer(MCContext &C,
-                                      std::unique_ptr<MCAsmBackend> MAB,
-                                      std::unique_ptr<MCObjectWriter> MOW,
-                                      std::unique_ptr<MCCodeEmitter> MCE);
+MCStreamer *createRISCVELFStreamer(const Triple &, MCContext &C,
+                                   std::unique_ptr<MCAsmBackend> &&MAB,
+                                   std::unique_ptr<MCObjectWriter> &&MOW,
+                                   std::unique_ptr<MCCodeEmitter> &&MCE);
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVELFSTREAMER_H

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

@@ -340,16 +340,6 @@ static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
   return new RISCVMCInstrAnalysis(Info);
 }
 
-namespace {
-MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context,
-                                   std::unique_ptr<MCAsmBackend> &&MAB,
-                                   std::unique_ptr<MCObjectWriter> &&MOW,
-                                   std::unique_ptr<MCCodeEmitter> &&MCE) {
-  return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
-                                std::move(MCE));
-}
-} // end anonymous namespace
-
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);