@@ -85,3 +85,98 @@ int test(int a, int b, int c, int d, int e, int f) {
8585// MCDC: %[[BITS:.+]] = load i8, ptr %[[LAB4]], align 1
8686// MCDC: %[[LAB8:[0-9]+]] = or i8 %[[BITS]], %[[LAB7]]
8787// MCDC: store i8 %[[LAB8]], ptr %[[LAB4]], align 1
88+
89+ int internot (int a , int b , int c , int d , int e , int f ) {
90+ return !(!(!a && b ) || !(!!(!c && d ) || !(e && !f )));
91+ }
92+
93+ // MCDC-LABEL: @internot(
94+ // MCDC-DAG: store i32 0, ptr %mcdc.addr, align 4
95+
96+ // Branch #2, (#0 - #2) [1,3,0]
97+ // !a [+0 => b][+6 => END]
98+ // MCDC-DAG: %[[A:.+]] = load i32, ptr %a.addr, align 4
99+ // MCDC-DAG: %[[AB:.+]] = icmp ne i32 %[[A]], 0
100+ // MCDC-DAG: %[[AN:.+]] = xor i1 %[[AB]], true
101+ // MCDC-DAG: %[[M1:.+]] = load i32, ptr %mcdc.addr, align 4
102+ // MCDC-DAG: %[[M1T:.+]] = add i32 %[[M1]], 0
103+ // MCDC-DAG: %[[M1F:.+]] = add i32 %[[M1]], 6
104+ // MCDC-DAG: %[[M1S:.+]] = select i1 %[[AN]], i32 %[[M1T]], i32 %[[M1F]]
105+ // MCDC-DAG: store i32 %[[M1S]], ptr %mcdc.addr, align 4
106+
107+ // Branch #3, (#2 - #3) [3,2,0]
108+ // b [+0 => c][+7 => END]
109+ // MCDC-DAG: %[[B:.+]] = load i32, ptr %b.addr, align 4
110+ // MCDC-DAG: %[[BB:.+]] = icmp ne i32 %[[B]], 0
111+ // MCDC-DAG: %[[M3:.+]] = load i32, ptr %mcdc.addr, align 4
112+ // MCDC-DAG: %[[M3T:.+]] = add i32 %[[M3]], 0
113+ // MCDC-DAG: %[[M3F:.+]] = add i32 %[[M3]], 7
114+ // MCDC-DAG: %[[M3S:.+]] = select i1 %[[BB]], i32 %[[M3T]], i32 %[[M3F]]
115+ // MCDC-DAG: store i32 %[[M3S]], ptr %mcdc.addr, align 4
116+
117+ // Branch #5, (#1 - #5) [2,5,4]
118+ // !c [+0 => d][+0 => e]
119+ // MCDC-DAG: %[[C:.+]] = load i32, ptr %c.addr, align 4
120+ // MCDC-DAG: %[[CB:.+]] = icmp ne i32 %[[C]], 0
121+ // MCDC-DAG: %[[CN:.+]] = xor i1 %[[CB]], true
122+ // MCDC-DAG: %[[M2:.+]] = load i32, ptr %mcdc.addr, align 4
123+ // MCDC-DAG: %[[M2T:.+]] = add i32 %[[M2]], 0
124+ // MCDC-DAG: %[[M2F:.+]] = add i32 %[[M2]], 0
125+ // MCDC-DAG: %[[M2S:.+]] = select i1 %[[CN]], i32 %[[M2T]], i32 %[[M2F]]
126+ // MCDC-DAG: store i32 %[[M2S]], ptr %mcdc.addr, align 4
127+
128+ // Branch #6, (#5 - #6) [5,0,4]
129+ // d [+8 => END][+1 => e]]
130+ // MCDC-DAG: %[[D:.+]] = load i32, ptr %d.addr, align 4
131+ // MCDC-DAG: %[[DB:.+]] = icmp ne i32 %[[D]], 0
132+ // MCDC-DAG: %[[M5:.+]] = load i32, ptr %mcdc.addr, align 4
133+ // MCDC-DAG: %[[M5T:.+]] = add i32 %[[M5]], 8
134+ // MCDC-DAG: %[[M5F:.+]] = add i32 %[[M5]], 1
135+ // MCDC-DAG: %[[M5S:.+]] = select i1 %[[DB]], i32 %[[M5T]], i32 %[[M5F]]
136+ // MCDC-DAG: store i32 %[[M5S]], ptr %mcdc.addr, align 4
137+
138+ // Branch #7, (#4 - #7) [4,6,0]
139+ // e [+0 => f][+0 => END]
140+ // from:
141+ // [c => +0]
142+ // [d => +1]
143+ // MCDC-DAG: %[[E:.+]] = load i32, ptr %e.addr, align 4
144+ // MCDC-DAG: %[[EB:.+]] = icmp ne i32 %[[E]], 0
145+ // MCDC-DAG: %[[M4:.+]] = load i32, ptr %mcdc.addr, align 4
146+ // MCDC-DAG: %[[M4T:.+]] = add i32 %[[M4]], 0
147+ // MCDC-DAG: %[[M4F:.+]] = add i32 %[[M4]], 0
148+ // MCDC-DAG: %[[M4S:.+]] = select i1 %[[EB]], i32 %[[M4T]], i32 %[[M4F]]
149+ // MCDC-DAG: store i32 %[[M4S]], ptr %mcdc.addr, align 4
150+
151+ // Branch #8, (#7 - #8) [6,0,0]
152+ // !f [+4 => END][+2 => END]
153+ // MCDC-DAG: %[[F:.+]] = load i32, ptr %f.addr, align 4
154+ // MCDC-DAG: %[[FB:.+]] = icmp ne i32 %[[F]], 0
155+ // MCDC-DAG: %[[FN:.+]] = xor i1 %[[FB]], true
156+ // MCDC-DAG: %[[M6:.+]] = load i32, ptr %mcdc.addr, align 4
157+ // MCDC-DAG: %[[M6T:.+]] = add i32 %[[M6]], 4
158+ // MCDC-DAG: %[[M6F:.+]] = add i32 %[[M6]], 2
159+ // MCDC-DAG: %[[M6S:.+]] = select i1 %[[FN]], i32 %[[M6T]], i32 %[[M6F]]
160+ // MCDC-DAG: store i32 %[[M6S]], ptr %mcdc.addr, align 4
161+
162+ // from:
163+ // [e => +0]
164+ // [f => +2]
165+ // [c => +0]
166+ // [d => +1]
167+ // [f => +4]
168+ // [c => +0]
169+ // [d => +1]
170+ // [a => +6]
171+ // [b => +7]
172+ // [d => +8]
173+ // MCDC-DAG: %[[T0:.+]] = load i32, ptr %mcdc.addr, align 4
174+ // MCDC-DAG: %[[T:.+]] = add i32 %[[T0]], 0
175+ // MCDC-DAG: %[[TA:.+]] = lshr i32 %[[T]], 3
176+ // MCDC-DAG: %[[BA:.+]] = getelementptr inbounds i8, ptr @__profbm_internot, i32 %[[TA]]
177+ // MCDC-DAG: %[[BI:.+]] = and i32 %[[T]], 7
178+ // MCDC-DAG: %[[BI1:.+]] = trunc i32 %[[BI]] to i8
179+ // MCDC-DAG: %[[BM:.+]] = shl i8 1, %[[BI1]]
180+ // MCDC-DAG: %mcdc.bits = load i8, ptr %[[BA]], align 1
181+ // MCDC-DAG: %[[BN:.+]] = or i8 %mcdc.bits, %[[BM]]
182+ // MCDC-DAG: store i8 %[[BN]], ptr %[[BA]], align 1
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