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[LV] Delete dead scalar loops (WIP).
Directly delete dead scalar loops after vectorization. The main benefit is follow-up optimizations not having to deal with dead code. There is no notable compile-time improvements for CTMark, although there may be benefits for code where a large number of loops are vectorized. The main benefit is more compact test checks. I've only updated a subset of failing tests and the code itself needs more polishing, but I wanted to share this early to see if this is desirable in general before going ahead and updating all tests.
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lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp‎

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@
8080
#include "llvm/Analysis/CFG.h"
8181
#include "llvm/Analysis/CodeMetrics.h"
8282
#include "llvm/Analysis/DemandedBits.h"
83+
#include "llvm/Analysis/DomTreeUpdater.h"
8384
#include "llvm/Analysis/GlobalsModRef.h"
8485
#include "llvm/Analysis/LoopAccessAnalysis.h"
8586
#include "llvm/Analysis/LoopAnalysisManager.h"
@@ -608,6 +609,29 @@ class InnerLoopVectorizer {
608609
/// count of the original loop for both main loop and epilogue vectorization.
609610
void setTripCount(Value *TC) { TripCount = TC; }
610611

612+
BasicBlock *getMiddleBlock() { return LoopMiddleBlock; }
613+
614+
BasicBlock *getMinIterBlock() {
615+
return LoopBypassBlocks.size() == 1 ? LoopBypassBlocks[0] : nullptr;
616+
}
617+
618+
bool isOriginalLoopDead() {
619+
auto *MinIter = getMinIterBlock();
620+
if (!MinIter)
621+
return false;
622+
{
623+
auto BI = cast<BranchInst>(MinIter->getTerminator());
624+
if (!BI->isConditional() ||
625+
BI->getCondition() !=
626+
ConstantInt::get(BI->getCondition()->getType(), 0))
627+
return false;
628+
}
629+
auto *BI = cast<BranchInst>(LoopMiddleBlock->getTerminator());
630+
return BI->isConditional() &&
631+
BI->getCondition() ==
632+
ConstantInt::get(BI->getCondition()->getType(), 1);
633+
}
634+
611635
protected:
612636
friend class LoopVectorizationPlanner;
613637

@@ -10151,6 +10175,10 @@ bool LoopVectorizePass::processLoop(Loop *L) {
1015110175

1015210176
bool DisableRuntimeUnroll = false;
1015310177
MDNode *OrigLoopID = L->getLoopID();
10178+
10179+
bool IsOriginalLoopDead = false;
10180+
BasicBlock *MiddleBlock = nullptr;
10181+
BasicBlock *MinIterBlock = nullptr;
1015410182
{
1015510183
using namespace ore;
1015610184
if (!VectorizeLoop) {
@@ -10268,6 +10296,10 @@ bool LoopVectorizePass::processLoop(Loop *L) {
1026810296
LVP.executePlan(VF.Width, IC, BestPlan, LB, DT, false);
1026910297
++LoopsVectorized;
1027010298

10299+
IsOriginalLoopDead = LB.isOriginalLoopDead();
10300+
MiddleBlock = LB.getMiddleBlock();
10301+
MinIterBlock = LB.getMinIterBlock();
10302+
1027110303
// Add metadata to disable runtime unrolling a scalar loop when there
1027210304
// are no runtime checks about strides and memory. A scalar loop that is
1027310305
// rarely used is not worth unrolling.
@@ -10295,7 +10327,36 @@ bool LoopVectorizePass::processLoop(Loop *L) {
1029510327
Hints.setAlreadyVectorized();
1029610328
}
1029710329

10298-
assert(!verifyFunction(*L->getHeader()->getParent(), &dbgs()));
10330+
if (IsOriginalLoopDead) {
10331+
auto *Br = cast<BranchInst>(MiddleBlock->getTerminator());
10332+
for (PHINode &PN : L->getExitBlock()->phis()) {
10333+
for (unsigned I = 0; I != PN.getNumIncomingValues(); ++I) {
10334+
if (LI->getLoopFor(PN.getIncomingBlock(I)) != L)
10335+
continue;
10336+
PN.setIncomingValue(I, UndefValue::get(PN.getType()));
10337+
}
10338+
}
10339+
10340+
formDedicatedExitBlocks(L, DT, LI, nullptr, true);
10341+
deleteDeadLoop(L, DT, SE, LI);
10342+
BasicBlock *PH = Br->getSuccessor(1);
10343+
BasicBlock *Exit = PH->getSingleSuccessor();
10344+
10345+
BranchInst::Create(Br->getSuccessor(0), MiddleBlock);
10346+
Br->eraseFromParent();
10347+
10348+
auto *Br2 = cast<BranchInst>(MinIterBlock->getTerminator());
10349+
BranchInst::Create(Br2->getSuccessor(1), MinIterBlock);
10350+
Br2->eraseFromParent();
10351+
10352+
LI->removeBlock(PH);
10353+
LI->removeBlock(Exit);
10354+
10355+
DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy);
10356+
DeleteDeadBlocks({PH, Exit}, &DTU);
10357+
}
10358+
10359+
assert(!verifyFunction(*F, &dbgs()));
1029910360
return true;
1030010361
}
1030110362

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll‎

Lines changed: 174 additions & 301 deletions
Large diffs are not rendered by default.

‎llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll‎

Lines changed: 13 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -207,7 +207,7 @@ define void @simple_memset_tailfold(i32 %val, ptr %ptr, i64 %n) "target-features
207207
; DATA_AND_CONTROL_NO_RT_CHECK-LABEL: @simple_memset_tailfold(
208208
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: entry:
209209
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1)
210-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
210+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br label [[VECTOR_PH:%.*]]
211211
; DATA_AND_CONTROL_NO_RT_CHECK: vector.ph:
212212
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
213213
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4
@@ -217,41 +217,31 @@ define void @simple_memset_tailfold(i32 %val, ptr %ptr, i64 %n) "target-features
217217
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], [[TMP4]]
218218
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]]
219219
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
220-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()
221-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 4
222220
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
223221
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 4
224-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[UMAX]], [[TMP6]]
225-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[UMAX]], [[TMP6]]
226-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP7]], i64 0
222+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
223+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 4
224+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[UMAX]], [[TMP8]]
225+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[UMAX]], [[TMP8]]
226+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 0
227227
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[UMAX]])
228228
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i64 0
229229
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
230230
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
231231
; DATA_AND_CONTROL_NO_RT_CHECK: vector.body:
232232
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VECTOR_BODY]] ]
233233
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ]
234-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX1]], 0
235-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[TMP10]]
236-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP11]], i32 0
237-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr [[TMP12]], i32 4, <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])
238-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[INDEX_NEXT2]] = add i64 [[INDEX1]], [[TMP14]]
239-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX1]], i64 [[TMP9]])
234+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX1]], 0
235+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 [[TMP12]]
236+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP13]], i32 0
237+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[BROADCAST_SPLAT]], ptr [[TMP14]], i32 4, <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])
238+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[INDEX_NEXT2]] = add i64 [[INDEX1]], [[TMP6]]
239+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX1]], i64 [[TMP11]])
240240
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP15:%.*]] = xor <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer)
241241
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 4 x i1> [[TMP15]], i32 0
242242
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
243243
; DATA_AND_CONTROL_NO_RT_CHECK: middle.block:
244-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br i1 true, label [[WHILE_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]
245-
; DATA_AND_CONTROL_NO_RT_CHECK: scalar.ph:
246-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
247-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br label [[WHILE_BODY:%.*]]
248-
; DATA_AND_CONTROL_NO_RT_CHECK: while.body:
249-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
250-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[INDEX]]
251-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: store i32 [[VAL]], ptr [[GEP]], align 4
252-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[INDEX_NEXT]] = add nsw i64 [[INDEX]], 1
253-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: [[CMP10:%.*]] = icmp ult i64 [[INDEX_NEXT]], [[N]]
254-
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br i1 [[CMP10]], label [[WHILE_BODY]], label [[WHILE_END_LOOPEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
244+
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: br label [[WHILE_END_LOOPEXIT:%.*]]
255245
; DATA_AND_CONTROL_NO_RT_CHECK: while.end.loopexit:
256246
; DATA_AND_CONTROL_NO_RT_CHECK-NEXT: ret void
257247
;

‎llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll‎

Lines changed: 5 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ define void @test0(ptr noalias %M3, ptr noalias %A, ptr noalias %B) {
88
; CHECK-LABEL: define void @test0
99
; CHECK-SAME: (ptr noalias [[M3:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) {
1010
; CHECK-NEXT: entry:
11-
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
11+
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
1212
; CHECK: vector.ph:
1313
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
1414
; CHECK: vector.body:
@@ -49,25 +49,7 @@ define void @test0(ptr noalias %M3, ptr noalias %A, ptr noalias %B) {
4949
; CHECK-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
5050
; CHECK-NEXT: br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
5151
; CHECK: middle.block:
52-
; CHECK-NEXT: br i1 true, label [[FOR_INC1286_LOOPEXIT:%.*]], label [[SCALAR_PH]]
53-
; CHECK: scalar.ph:
54-
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
55-
; CHECK-NEXT: br label [[IF_THEN1165_US:%.*]]
56-
; CHECK: if.then1165.us:
57-
; CHECK-NEXT: [[INDVARS_IV1783:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT1784:%.*]], [[IF_THEN1165_US]] ]
58-
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i16, ptr [[A]], i64 [[INDVARS_IV1783]]
59-
; CHECK-NEXT: [[L_A:%.*]] = load i16, ptr [[GEP_A]], align 2
60-
; CHECK-NEXT: [[CONV1177_US:%.*]] = zext i16 [[L_A]] to i32
61-
; CHECK-NEXT: [[ADD1178_US:%.*]] = add nsw i32 [[CONV1177_US]], 10
62-
; CHECK-NEXT: [[CONV1179_US:%.*]] = trunc i32 [[ADD1178_US]] to i16
63-
; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDVARS_IV1783]]
64-
; CHECK-NEXT: [[L_B:%.*]] = load i64, ptr [[GEP_B]], align 8
65-
; CHECK-NEXT: [[IDXPROM1181_US:%.*]] = ashr exact i64 [[L_B]], 32
66-
; CHECK-NEXT: [[ARRAYIDX1185_US:%.*]] = getelementptr inbounds i16, ptr [[M3]], i64 [[IDXPROM1181_US]]
67-
; CHECK-NEXT: store i16 [[CONV1179_US]], ptr [[ARRAYIDX1185_US]], align 2
68-
; CHECK-NEXT: [[INDVARS_IV_NEXT1784]] = add nuw nsw i64 [[INDVARS_IV1783]], 1
69-
; CHECK-NEXT: [[EXITCOND1785:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT1784]], 16
70-
; CHECK-NEXT: br i1 [[EXITCOND1785]], label [[FOR_INC1286_LOOPEXIT]], label [[IF_THEN1165_US]], !llvm.loop [[LOOP3:![0-9]+]]
52+
; CHECK-NEXT: br label [[FOR_INC1286_LOOPEXIT:%.*]]
7153
; CHECK: for.inc1286.loopexit:
7254
; CHECK-NEXT: ret void
7355
;
@@ -98,7 +80,7 @@ define void @test1(ptr noalias %M3, ptr noalias %A, ptr noalias %B, ptr noalias
9880
; CHECK-LABEL: define void @test1
9981
; CHECK-SAME: (ptr noalias [[M3:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) {
10082
; CHECK-NEXT: entry:
101-
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
83+
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
10284
; CHECK: vector.ph:
10385
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
10486
; CHECK: vector.body:
@@ -141,28 +123,9 @@ define void @test1(ptr noalias %M3, ptr noalias %A, ptr noalias %B, ptr noalias
141123
; CHECK-NEXT: store i16 [[TMP28]], ptr [[TMP24]], align 2
142124
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
143125
; CHECK-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
144-
; CHECK-NEXT: br i1 [[TMP29]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
126+
; CHECK-NEXT: br i1 [[TMP29]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
145127
; CHECK: middle.block:
146-
; CHECK-NEXT: br i1 true, label [[FOR_INC1286_LOOPEXIT:%.*]], label [[SCALAR_PH]]
147-
; CHECK: scalar.ph:
148-
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
149-
; CHECK-NEXT: br label [[IF_THEN1165_US:%.*]]
150-
; CHECK: if.then1165.us:
151-
; CHECK-NEXT: [[INDVARS_IV1783:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT1784:%.*]], [[IF_THEN1165_US]] ]
152-
; CHECK-NEXT: [[FPTR:%.*]] = load i32, ptr [[C]], align 4
153-
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i16, ptr [[A]], i64 [[INDVARS_IV1783]]
154-
; CHECK-NEXT: [[L_A:%.*]] = load i16, ptr [[GEP_A]], align 2
155-
; CHECK-NEXT: [[CONV1177_US:%.*]] = zext i16 [[L_A]] to i32
156-
; CHECK-NEXT: [[ADD1178_US:%.*]] = add nsw i32 [[CONV1177_US]], [[FPTR]]
157-
; CHECK-NEXT: [[CONV1179_US:%.*]] = trunc i32 [[ADD1178_US]] to i16
158-
; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDVARS_IV1783]]
159-
; CHECK-NEXT: [[L_B:%.*]] = load i64, ptr [[GEP_B]], align 8
160-
; CHECK-NEXT: [[IDXPROM1181_US:%.*]] = ashr exact i64 [[L_B]], 32
161-
; CHECK-NEXT: [[ARRAYIDX1185_US:%.*]] = getelementptr inbounds i16, ptr [[M3]], i64 [[IDXPROM1181_US]]
162-
; CHECK-NEXT: store i16 [[CONV1179_US]], ptr [[ARRAYIDX1185_US]], align 2
163-
; CHECK-NEXT: [[INDVARS_IV_NEXT1784]] = add nuw nsw i64 [[INDVARS_IV1783]], 1
164-
; CHECK-NEXT: [[EXITCOND1785:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT1784]], 16
165-
; CHECK-NEXT: br i1 [[EXITCOND1785]], label [[FOR_INC1286_LOOPEXIT]], label [[IF_THEN1165_US]], !llvm.loop [[LOOP5:![0-9]+]]
128+
; CHECK-NEXT: br label [[FOR_INC1286_LOOPEXIT:%.*]]
166129
; CHECK: for.inc1286.loopexit:
167130
; CHECK-NEXT: ret void
168131
;

‎llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ attributes #0 = { "target-cpu"="knl" }
8181
;
8282
; FORCE-LABEL: @PR40816(
8383
; FORCE-NEXT: entry:
84-
; FORCE-NEXT: br i1 false, label {{%.*}}, label [[VECTOR_PH:%.*]]
84+
; FORCE-NEXT: br label [[VECTOR_PH:%.*]]
8585
; FORCE: vector.ph:
8686
; FORCE-NEXT: br label [[VECTOR_BODY:%.*]]
8787
; FORCE: vector.body:

‎llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll‎

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
define void @f1() {
1414
; CHECK-LABEL: @f1(
1515
; CHECK-NEXT: bb1:
16-
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
16+
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
1717
; CHECK: vector.ph:
1818
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
1919
; CHECK: vector.body:
@@ -27,20 +27,7 @@ define void @f1() {
2727
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
2828
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
2929
; CHECK: middle.block:
30-
; CHECK-NEXT: br i1 true, label [[BB3:%.*]], label [[SCALAR_PH]]
31-
; CHECK: scalar.ph:
32-
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 2, [[MIDDLE_BLOCK]] ], [ 0, [[BB1:%.*]] ]
33-
; CHECK-NEXT: br label [[BB2:%.*]]
34-
; CHECK: bb2:
35-
; CHECK-NEXT: [[C_1_0:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[_TMP9:%.*]], [[BB2]] ]
36-
; CHECK-NEXT: [[_TMP1:%.*]] = zext i16 0 to i64
37-
; CHECK-NEXT: [[_TMP2:%.*]] = getelementptr [1 x %rec8], ptr @a, i16 0, i64 [[_TMP1]]
38-
; CHECK-NEXT: [[_TMP6:%.*]] = sext i16 [[C_1_0]] to i64
39-
; CHECK-NEXT: [[_TMP7:%.*]] = getelementptr [2 x ptr], ptr @b, i16 0, i64 [[_TMP6]]
40-
; CHECK-NEXT: store ptr [[_TMP2]], ptr [[_TMP7]], align 8
41-
; CHECK-NEXT: [[_TMP9]] = add nsw i16 [[C_1_0]], 1
42-
; CHECK-NEXT: [[_TMP11:%.*]] = icmp slt i16 [[_TMP9]], 2
43-
; CHECK-NEXT: br i1 [[_TMP11]], label [[BB2]], label [[BB3]], !llvm.loop [[LOOP2:![0-9]+]]
30+
; CHECK-NEXT: br label [[BB3:%.*]]
4431
; CHECK: bb3:
4532
; CHECK-NEXT: ret void
4633
;

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