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[RISCV] Fix incorrect use of TA in some tablegen class names. NFC
These either have an explicit policy operand or use TU policy.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 90 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -4237,16 +4237,16 @@ class VPatBinaryMask<string intrinsic_name,
42374237
(op2_type op2_kind:$rs2),
42384238
(mask_type V0), GPR:$vl, sew)>;
42394239

4240-
class VPatBinaryMaskTA<string intrinsic_name,
4241-
string inst,
4242-
ValueType result_type,
4243-
ValueType op1_type,
4244-
ValueType op2_type,
4245-
ValueType mask_type,
4246-
int sew,
4247-
VReg result_reg_class,
4248-
VReg op1_reg_class,
4249-
DAGOperand op2_kind> :
4240+
class VPatBinaryMaskPolicy<string intrinsic_name,
4241+
string inst,
4242+
ValueType result_type,
4243+
ValueType op1_type,
4244+
ValueType op2_type,
4245+
ValueType mask_type,
4246+
int sew,
4247+
VReg result_reg_class,
4248+
VReg op1_reg_class,
4249+
DAGOperand op2_kind> :
42504250
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
42514251
(result_type result_reg_class:$merge),
42524252
(op1_type op1_reg_class:$rs1),
@@ -4812,9 +4812,9 @@ multiclass VPatBinary<string intrinsic,
48124812
DAGOperand op2_kind> {
48134813
def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type,
48144814
sew, result_reg_class, op1_reg_class, op2_kind>;
4815-
def : VPatBinaryMaskTA<intrinsic, inst, result_type, op1_type, op2_type,
4816-
mask_type, sew, result_reg_class, op1_reg_class,
4817-
op2_kind>;
4815+
def : VPatBinaryMaskPolicy<intrinsic, inst, result_type, op1_type, op2_type,
4816+
mask_type, sew, result_reg_class, op1_reg_class,
4817+
op2_kind>;
48184818
}
48194819

48204820
multiclass VPatBinaryRoundingMode<string intrinsic,
@@ -4920,17 +4920,17 @@ multiclass VPatBinaryMaskOut<string intrinsic,
49204920
GPR:$vl, sew)>;
49214921
}
49224922

4923-
multiclass VPatConversionTA<string intrinsic,
4924-
string inst,
4925-
string kind,
4926-
ValueType result_type,
4927-
ValueType op1_type,
4928-
ValueType mask_type,
4929-
int log2sew,
4930-
LMULInfo vlmul,
4931-
VReg result_reg_class,
4932-
VReg op1_reg_class,
4933-
bit isSEWAware = 0> {
4923+
multiclass VPatConversion<string intrinsic,
4924+
string inst,
4925+
string kind,
4926+
ValueType result_type,
4927+
ValueType op1_type,
4928+
ValueType mask_type,
4929+
int log2sew,
4930+
LMULInfo vlmul,
4931+
VReg result_reg_class,
4932+
VReg op1_reg_class,
4933+
bit isSEWAware = 0> {
49344934
def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,
49354935
log2sew, vlmul, result_reg_class, op1_reg_class,
49364936
isSEWAware>;
@@ -4939,17 +4939,17 @@ multiclass VPatConversionTA<string intrinsic,
49394939
isSEWAware>;
49404940
}
49414941

4942-
multiclass VPatConversionTARoundingMode<string intrinsic,
4943-
string inst,
4944-
string kind,
4945-
ValueType result_type,
4946-
ValueType op1_type,
4947-
ValueType mask_type,
4948-
int log2sew,
4949-
LMULInfo vlmul,
4950-
VReg result_reg_class,
4951-
VReg op1_reg_class,
4952-
bit isSEWAware = 0> {
4942+
multiclass VPatConversionRoundingMode<string intrinsic,
4943+
string inst,
4944+
string kind,
4945+
ValueType result_type,
4946+
ValueType op1_type,
4947+
ValueType mask_type,
4948+
int log2sew,
4949+
LMULInfo vlmul,
4950+
VReg result_reg_class,
4951+
VReg op1_reg_class,
4952+
bit isSEWAware = 0> {
49534953
def : VPatUnaryNoMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type,
49544954
log2sew, vlmul, result_reg_class,
49554955
op1_reg_class, isSEWAware>;
@@ -5173,10 +5173,10 @@ multiclass VPatBinaryW_WV<string intrinsic, string instruction,
51735173
Wti.Vector, Vti.Vector, Vti.Mask,
51745174
Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;
51755175
}
5176-
def : VPatBinaryMaskTA<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5177-
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
5178-
Vti.Log2SEW, Wti.RegClass,
5179-
Wti.RegClass, Vti.RegClass>;
5176+
def : VPatBinaryMaskPolicy<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5177+
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
5178+
Vti.Log2SEW, Wti.RegClass,
5179+
Wti.RegClass, Vti.RegClass>;
51805180
}
51815181
}
51825182
}
@@ -5930,9 +5930,9 @@ multiclass VPatConversionVI_VF<string intrinsic,
59305930
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
59315931
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
59325932
GetVTypePredicates<ivti>.Predicates) in
5933-
defm : VPatConversionTA<intrinsic, instruction, "V",
5934-
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
5935-
fvti.LMul, ivti.RegClass, fvti.RegClass>;
5933+
defm : VPatConversion<intrinsic, instruction, "V",
5934+
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
5935+
fvti.LMul, ivti.RegClass, fvti.RegClass>;
59365936
}
59375937
}
59385938

@@ -5942,9 +5942,9 @@ multiclass VPatConversionVI_VF_RM<string intrinsic,
59425942
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
59435943
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
59445944
GetVTypePredicates<ivti>.Predicates) in
5945-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
5946-
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
5947-
fvti.LMul, ivti.RegClass, fvti.RegClass>;
5945+
defm : VPatConversionRoundingMode<intrinsic, instruction, "V",
5946+
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
5947+
fvti.LMul, ivti.RegClass, fvti.RegClass>;
59485948
}
59495949
}
59505950

@@ -5954,10 +5954,10 @@ multiclass VPatConversionVF_VI_RM<string intrinsic, string instruction,
59545954
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
59555955
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
59565956
GetVTypePredicates<ivti>.Predicates) in
5957-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
5958-
fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
5959-
ivti.LMul, fvti.RegClass, ivti.RegClass,
5960-
isSEWAware>;
5957+
defm : VPatConversionRoundingMode<intrinsic, instruction, "V",
5958+
fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
5959+
ivti.LMul, fvti.RegClass, ivti.RegClass,
5960+
isSEWAware>;
59615961
}
59625962
}
59635963

@@ -5967,9 +5967,9 @@ multiclass VPatConversionWI_VF<string intrinsic, string instruction> {
59675967
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
59685968
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
59695969
GetVTypePredicates<iwti>.Predicates) in
5970-
defm : VPatConversionTA<intrinsic, instruction, "V",
5971-
iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
5972-
fvti.LMul, iwti.RegClass, fvti.RegClass>;
5970+
defm : VPatConversion<intrinsic, instruction, "V",
5971+
iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
5972+
fvti.LMul, iwti.RegClass, fvti.RegClass>;
59735973
}
59745974
}
59755975

@@ -5979,9 +5979,9 @@ multiclass VPatConversionWI_VF_RM<string intrinsic, string instruction> {
59795979
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
59805980
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
59815981
GetVTypePredicates<iwti>.Predicates) in
5982-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
5983-
iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
5984-
fvti.LMul, iwti.RegClass, fvti.RegClass>;
5982+
defm : VPatConversionRoundingMode<intrinsic, instruction, "V",
5983+
iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,
5984+
fvti.LMul, iwti.RegClass, fvti.RegClass>;
59855985
}
59865986
}
59875987

@@ -5992,9 +5992,9 @@ multiclass VPatConversionWF_VI<string intrinsic, string instruction,
59925992
defvar fwti = vtiToWti.Wti;
59935993
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
59945994
GetVTypePredicates<fwti>.Predicates) in
5995-
defm : VPatConversionTA<intrinsic, instruction, "V",
5996-
fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
5997-
vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;
5995+
defm : VPatConversion<intrinsic, instruction, "V",
5996+
fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
5997+
vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;
59985998
}
59995999
}
60006000

@@ -6007,35 +6007,35 @@ multiclass VPatConversionWF_VF<string intrinsic, string instruction,
60076007
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
60086008
!listconcat(GetVTypePredicates<fvti>.Predicates,
60096009
GetVTypePredicates<fwti>.Predicates)) in
6010-
defm : VPatConversionTA<intrinsic, instruction, "V",
6011-
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
6012-
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
6010+
defm : VPatConversion<intrinsic, instruction, "V",
6011+
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
6012+
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
60136013
}
60146014
}
60156015

6016-
multiclass VPatConversionWF_VF_BF <string intrinsic, string instruction,
6017-
bit isSEWAware = 0> {
6016+
multiclass VPatConversionWF_VF_BF<string intrinsic, string instruction,
6017+
bit isSEWAware = 0> {
60186018
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in
60196019
{
60206020
defvar fvti = fvtiToFWti.Vti;
60216021
defvar fwti = fvtiToFWti.Wti;
60226022
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60236023
GetVTypePredicates<fwti>.Predicates) in
6024-
defm : VPatConversionTA<intrinsic, instruction, "V",
6025-
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
6026-
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
6024+
defm : VPatConversion<intrinsic, instruction, "V",
6025+
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
6026+
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
60276027
}
60286028
}
60296029

6030-
multiclass VPatConversionVI_WF <string intrinsic, string instruction> {
6030+
multiclass VPatConversionVI_WF<string intrinsic, string instruction> {
60316031
foreach vtiToWti = AllWidenableIntToFloatVectors in {
60326032
defvar vti = vtiToWti.Vti;
60336033
defvar fwti = vtiToWti.Wti;
60346034
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
60356035
GetVTypePredicates<fwti>.Predicates) in
6036-
defm : VPatConversionTA<intrinsic, instruction, "W",
6037-
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
6038-
vti.LMul, vti.RegClass, fwti.RegClass>;
6036+
defm : VPatConversion<intrinsic, instruction, "W",
6037+
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
6038+
vti.LMul, vti.RegClass, fwti.RegClass>;
60396039
}
60406040
}
60416041

@@ -6045,9 +6045,9 @@ multiclass VPatConversionVI_WF_RM <string intrinsic, string instruction> {
60456045
defvar fwti = vtiToWti.Wti;
60466046
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
60476047
GetVTypePredicates<fwti>.Predicates) in
6048-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
6049-
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
6050-
vti.LMul, vti.RegClass, fwti.RegClass>;
6048+
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
6049+
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
6050+
vti.LMul, vti.RegClass, fwti.RegClass>;
60516051
}
60526052
}
60536053

@@ -6058,10 +6058,10 @@ multiclass VPatConversionVF_WI_RM <string intrinsic, string instruction,
60586058
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
60596059
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60606060
GetVTypePredicates<iwti>.Predicates) in
6061-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
6062-
fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
6063-
fvti.LMul, fvti.RegClass, iwti.RegClass,
6064-
isSEWAware>;
6061+
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
6062+
fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
6063+
fvti.LMul, fvti.RegClass, iwti.RegClass,
6064+
isSEWAware>;
60656065
}
60666066
}
60676067

@@ -6072,9 +6072,9 @@ multiclass VPatConversionVF_WF<string intrinsic, string instruction,
60726072
defvar fwti = fvtiToFWti.Wti;
60736073
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60746074
GetVTypePredicates<fwti>.Predicates) in
6075-
defm : VPatConversionTA<intrinsic, instruction, "W",
6076-
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6077-
fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
6075+
defm : VPatConversion<intrinsic, instruction, "W",
6076+
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6077+
fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
60786078
}
60796079
}
60806080

@@ -6086,24 +6086,24 @@ multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,
60866086
defvar fwti = fvtiToFWti.Wti;
60876087
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60886088
GetVTypePredicates<fwti>.Predicates) in
6089-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
6090-
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6091-
fvti.LMul, fvti.RegClass, fwti.RegClass,
6092-
isSEWAware>;
6089+
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
6090+
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6091+
fvti.LMul, fvti.RegClass, fwti.RegClass,
6092+
isSEWAware>;
60936093
}
60946094
}
60956095

6096-
multiclass VPatConversionVF_WF_BF_RM <string intrinsic, string instruction,
6097-
bit isSEWAware = 0> {
6096+
multiclass VPatConversionVF_WF_BF_RM<string intrinsic, string instruction,
6097+
bit isSEWAware = 0> {
60986098
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
60996099
defvar fvti = fvtiToFWti.Vti;
61006100
defvar fwti = fvtiToFWti.Wti;
61016101
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
61026102
GetVTypePredicates<fwti>.Predicates) in
6103-
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
6104-
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6105-
fvti.LMul, fvti.RegClass, fwti.RegClass,
6106-
isSEWAware>;
6103+
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
6104+
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6105+
fvti.LMul, fvti.RegClass, fwti.RegClass,
6106+
isSEWAware>;
61076107
}
61086108
}
61096109

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