[RISCV] make SRLW io types be 64 bits

Signed-off-by: Shreeyash Pandey <[email protected]>

Author: bojle

llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp

@@ -94,8 +94,8 @@ TEST_F(RISCVSelectionDAGTest, computeKnownBits_SRLW) {
   auto Px = DAG->getRegister(0, IntVT);
   auto Py = DAG->getConstant(2147483647, Loc, IntVT);
   auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Px, Py);
-  auto Qx = DAG->getRegister(0, IntVT);
-  auto N2 = DAG->getNode(RISCVISD::SRLW, Loc, IntVT, N1, Qx);
+  auto Qx = DAG->getRegister(0, Int64VT);
+  auto N2 = DAG->getNode(RISCVISD::SRLW, Loc, Int64VT, N1, Qx);
   auto N3 = DAG->getNode(ISD::ZERO_EXTEND, Loc, Int64VT, N2);
   // N1 = 0???????????????????????????????
   // N2 = 0???????????????????????????????