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[AggressiveInstCombine] Add more tests. NFC.
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‎llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll‎

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1790,6 +1790,136 @@ define i16 @loadCombine_mixsize_4bit(ptr %p) {
17901790
ret i16 %o2
17911791
}
17921792

1793+
define i32 @loadCombine_2consecutive_mixsize_4bit(ptr %p) {
1794+
; ALL-LABEL: @loadCombine_2consecutive_mixsize_4bit(
1795+
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 1
1796+
; ALL-NEXT: [[L1:%.*]] = load i4, ptr [[P]], align 1
1797+
; ALL-NEXT: [[L2:%.*]] = load i28, ptr [[P1]], align 4
1798+
; ALL-NEXT: [[E1:%.*]] = zext i4 [[L1]] to i32
1799+
; ALL-NEXT: [[E2:%.*]] = zext i28 [[L2]] to i32
1800+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 4
1801+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1802+
; ALL-NEXT: ret i32 [[O1]]
1803+
;
1804+
%p1 = getelementptr i4, ptr %p, i32 1
1805+
%l1 = load i4, ptr %p
1806+
%l2 = load i28, ptr %p1
1807+
%e1 = zext i4 %l1 to i32
1808+
%e2 = zext i28 %l2 to i32
1809+
%s2 = shl i32 %e2, 4
1810+
%o1 = or i32 %e1, %s2
1811+
ret i32 %o1
1812+
}
1813+
1814+
define i32 @loadCombine_2consecutive_mixsize_4bit2(ptr %p) {
1815+
; ALL-LABEL: @loadCombine_2consecutive_mixsize_4bit2(
1816+
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 7
1817+
; ALL-NEXT: [[L1:%.*]] = load i28, ptr [[P]], align 4
1818+
; ALL-NEXT: [[L2:%.*]] = load i4, ptr [[P1]], align 1
1819+
; ALL-NEXT: [[E1:%.*]] = zext i28 [[L1]] to i32
1820+
; ALL-NEXT: [[E2:%.*]] = zext i4 [[L2]] to i32
1821+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 28
1822+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1823+
; ALL-NEXT: ret i32 [[O1]]
1824+
;
1825+
%p1 = getelementptr i4, ptr %p, i32 7
1826+
%l1 = load i28, ptr %p
1827+
%l2 = load i4, ptr %p1
1828+
%e1 = zext i28 %l1 to i32
1829+
%e2 = zext i4 %l2 to i32
1830+
%s2 = shl i32 %e2, 28
1831+
%o1 = or i32 %e1, %s2
1832+
ret i32 %o1
1833+
}
1834+
1835+
define i32 @loadCombine_2consecutive_mixsize_not_power_of_two(ptr %p) {
1836+
; LE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two(
1837+
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
1838+
; LE-NEXT: ret i32 [[L1]]
1839+
;
1840+
; BE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two(
1841+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1842+
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1843+
; BE-NEXT: [[L2:%.*]] = load i24, ptr [[P1]], align 4
1844+
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1845+
; BE-NEXT: [[E2:%.*]] = zext i24 [[L2]] to i32
1846+
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1847+
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1848+
; BE-NEXT: ret i32 [[O1]]
1849+
;
1850+
%p1 = getelementptr i8, ptr %p, i32 1
1851+
%l1 = load i8, ptr %p
1852+
%l2 = load i24, ptr %p1
1853+
%e1 = zext i8 %l1 to i32
1854+
%e2 = zext i24 %l2 to i32
1855+
%s2 = shl i32 %e2, 8
1856+
%o1 = or i32 %e1, %s2
1857+
ret i32 %o1
1858+
}
1859+
1860+
define i32 @loadCombine_2consecutive_mixsize_not_power_of_two2(ptr %p) {
1861+
; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two2(
1862+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3
1863+
; ALL-NEXT: [[L1:%.*]] = load i24, ptr [[P]], align 4
1864+
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1865+
; ALL-NEXT: [[E1:%.*]] = zext i24 [[L1]] to i32
1866+
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1867+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 24
1868+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1869+
; ALL-NEXT: ret i32 [[O1]]
1870+
;
1871+
%p1 = getelementptr i8, ptr %p, i32 3
1872+
%l1 = load i24, ptr %p
1873+
%l2 = load i8, ptr %p1
1874+
%e1 = zext i24 %l1 to i32
1875+
%e2 = zext i8 %l2 to i32
1876+
%s2 = shl i32 %e2, 24
1877+
%o1 = or i32 %e1, %s2
1878+
ret i32 %o1
1879+
}
1880+
1881+
define i32 @loadCombine_2consecutive_sum_size_not_legal(ptr %p) {
1882+
; ALL-LABEL: @loadCombine_2consecutive_sum_size_not_legal(
1883+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1884+
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1885+
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1886+
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1887+
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1888+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
1889+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1890+
; ALL-NEXT: ret i32 [[O1]]
1891+
;
1892+
%p1 = getelementptr i8, ptr %p, i32 2
1893+
%l1 = load i16, ptr %p
1894+
%l2 = load i8, ptr %p1
1895+
%e1 = zext i16 %l1 to i32
1896+
%e2 = zext i8 %l2 to i32
1897+
%s2 = shl i32 %e2, 16
1898+
%o1 = or i32 %e1, %s2
1899+
ret i32 %o1
1900+
}
1901+
1902+
define i32 @loadCombine_2consecutive_sum_size_not_legal2(ptr %p) {
1903+
; ALL-LABEL: @loadCombine_2consecutive_sum_size_not_legal2(
1904+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1905+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1906+
; ALL-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
1907+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1908+
; ALL-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
1909+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1910+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1911+
; ALL-NEXT: ret i32 [[O1]]
1912+
;
1913+
%p1 = getelementptr i8, ptr %p, i32 1
1914+
%l1 = load i8, ptr %p
1915+
%l2 = load i16, ptr %p1
1916+
%e1 = zext i8 %l1 to i32
1917+
%e2 = zext i16 %l2 to i32
1918+
%s2 = shl i32 %e2, 8
1919+
%o1 = or i32 %e1, %s2
1920+
ret i32 %o1
1921+
}
1922+
17931923
define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
17941924
; LE-LABEL: @loadCombine_8consecutive_mixsize(
17951925
; LE-NEXT: [[L1:%.*]] = load i64, ptr [[P:%.*]], align 1

‎llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll‎

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1874,6 +1874,136 @@ define i16 @loadCombine_mixsize_4bit(ptr %p) {
18741874
ret i16 %o2
18751875
}
18761876

1877+
define i32 @loadCombine_2consecutive_mixsize_4bit(ptr %p) {
1878+
; ALL-LABEL: @loadCombine_2consecutive_mixsize_4bit(
1879+
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 1
1880+
; ALL-NEXT: [[L1:%.*]] = load i4, ptr [[P]], align 1
1881+
; ALL-NEXT: [[L2:%.*]] = load i28, ptr [[P1]], align 4
1882+
; ALL-NEXT: [[E1:%.*]] = zext i4 [[L1]] to i32
1883+
; ALL-NEXT: [[E2:%.*]] = zext i28 [[L2]] to i32
1884+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 4
1885+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1886+
; ALL-NEXT: ret i32 [[O1]]
1887+
;
1888+
%p1 = getelementptr i4, ptr %p, i32 1
1889+
%l1 = load i4, ptr %p
1890+
%l2 = load i28, ptr %p1
1891+
%e1 = zext i4 %l1 to i32
1892+
%e2 = zext i28 %l2 to i32
1893+
%s2 = shl i32 %e2, 4
1894+
%o1 = or i32 %e1, %s2
1895+
ret i32 %o1
1896+
}
1897+
1898+
define i32 @loadCombine_2consecutive_mixsize_4bit2(ptr %p) {
1899+
; ALL-LABEL: @loadCombine_2consecutive_mixsize_4bit2(
1900+
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 7
1901+
; ALL-NEXT: [[L1:%.*]] = load i28, ptr [[P]], align 4
1902+
; ALL-NEXT: [[L2:%.*]] = load i4, ptr [[P1]], align 1
1903+
; ALL-NEXT: [[E1:%.*]] = zext i28 [[L1]] to i32
1904+
; ALL-NEXT: [[E2:%.*]] = zext i4 [[L2]] to i32
1905+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 28
1906+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1907+
; ALL-NEXT: ret i32 [[O1]]
1908+
;
1909+
%p1 = getelementptr i4, ptr %p, i32 7
1910+
%l1 = load i28, ptr %p
1911+
%l2 = load i4, ptr %p1
1912+
%e1 = zext i28 %l1 to i32
1913+
%e2 = zext i4 %l2 to i32
1914+
%s2 = shl i32 %e2, 28
1915+
%o1 = or i32 %e1, %s2
1916+
ret i32 %o1
1917+
}
1918+
1919+
define i32 @loadCombine_2consecutive_mixsize_not_power_of_two(ptr %p) {
1920+
; LE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two(
1921+
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
1922+
; LE-NEXT: ret i32 [[L1]]
1923+
;
1924+
; BE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two(
1925+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1926+
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1927+
; BE-NEXT: [[L2:%.*]] = load i24, ptr [[P1]], align 4
1928+
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1929+
; BE-NEXT: [[E2:%.*]] = zext i24 [[L2]] to i32
1930+
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1931+
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1932+
; BE-NEXT: ret i32 [[O1]]
1933+
;
1934+
%p1 = getelementptr i8, ptr %p, i32 1
1935+
%l1 = load i8, ptr %p
1936+
%l2 = load i24, ptr %p1
1937+
%e1 = zext i8 %l1 to i32
1938+
%e2 = zext i24 %l2 to i32
1939+
%s2 = shl i32 %e2, 8
1940+
%o1 = or i32 %e1, %s2
1941+
ret i32 %o1
1942+
}
1943+
1944+
define i32 @loadCombine_2consecutive_mixsize_not_power_of_two2(ptr %p) {
1945+
; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two2(
1946+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3
1947+
; ALL-NEXT: [[L1:%.*]] = load i24, ptr [[P]], align 4
1948+
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1949+
; ALL-NEXT: [[E1:%.*]] = zext i24 [[L1]] to i32
1950+
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1951+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 24
1952+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1953+
; ALL-NEXT: ret i32 [[O1]]
1954+
;
1955+
%p1 = getelementptr i8, ptr %p, i32 3
1956+
%l1 = load i24, ptr %p
1957+
%l2 = load i8, ptr %p1
1958+
%e1 = zext i24 %l1 to i32
1959+
%e2 = zext i8 %l2 to i32
1960+
%s2 = shl i32 %e2, 24
1961+
%o1 = or i32 %e1, %s2
1962+
ret i32 %o1
1963+
}
1964+
1965+
define i32 @loadCombine_2consecutive_sum_size_not_legal(ptr %p) {
1966+
; ALL-LABEL: @loadCombine_2consecutive_sum_size_not_legal(
1967+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1968+
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1969+
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1970+
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1971+
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1972+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
1973+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1974+
; ALL-NEXT: ret i32 [[O1]]
1975+
;
1976+
%p1 = getelementptr i8, ptr %p, i32 2
1977+
%l1 = load i16, ptr %p
1978+
%l2 = load i8, ptr %p1
1979+
%e1 = zext i16 %l1 to i32
1980+
%e2 = zext i8 %l2 to i32
1981+
%s2 = shl i32 %e2, 16
1982+
%o1 = or i32 %e1, %s2
1983+
ret i32 %o1
1984+
}
1985+
1986+
define i32 @loadCombine_2consecutive_sum_size_not_legal2(ptr %p) {
1987+
; ALL-LABEL: @loadCombine_2consecutive_sum_size_not_legal2(
1988+
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1989+
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1990+
; ALL-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
1991+
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1992+
; ALL-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
1993+
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1994+
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1995+
; ALL-NEXT: ret i32 [[O1]]
1996+
;
1997+
%p1 = getelementptr i8, ptr %p, i32 1
1998+
%l1 = load i8, ptr %p
1999+
%l2 = load i16, ptr %p1
2000+
%e1 = zext i8 %l1 to i32
2001+
%e2 = zext i16 %l2 to i32
2002+
%s2 = shl i32 %e2, 8
2003+
%o1 = or i32 %e1, %s2
2004+
ret i32 %o1
2005+
}
2006+
18772007
define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
18782008
; LE-LABEL: @loadCombine_8consecutive_mixsize(
18792009
; LE-NEXT: [[O3:%.*]] = load i64, ptr [[P:%.*]], align 1

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