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[clang][x86] Add C/C++ and 32/64-bit test coverage to constexpr tests (#152478)
Adds missing C++ run lines to test files containing `constexpr` tests. Also adds missing 32/64-bit test coverage to the following tests: - `clang/test/CodeGen/X86/avx512-reduceIntrin.c` - `clang/test/CodeGen/X86/avx512-reduceMinMaxIntrin.c` - `clang/test/CodeGen/X86/avx512vpopcntdq-builtins.c` - `clang/test/CodeGen/X86/avx512vpopcntdqvl-builtins.c` Additionally, fixes a `_mm512_popcnt_epi64` `constexpr` test that incorrectly assumed 32-bit integers, leading to incorrect bit counts. This change updates the test result to assume 64-bit integers.
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‎clang/test/CodeGen/X86/avx512-reduceIntrin.c‎

Lines changed: 51 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,171 +1,174 @@
1-
// RUN: %clang_cc1 -ffreestanding %s -O0 -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
1+
// RUN: %clang_cc1 -x c -ffreestanding %s -O0 -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
2+
// RUN: %clang_cc1 -x c -ffreestanding %s -O0 -triple=i386-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
3+
// RUN: %clang_cc1 -x c++ -ffreestanding %s -O0 -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
4+
// RUN: %clang_cc1 -x c++ -ffreestanding %s -O0 -triple=i386-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
25

36
#include <immintrin.h>
47
#include "builtin_test_helpers.h"
58

69
long long test_mm512_reduce_add_epi64(__m512i __W){
7-
// CHECK-LABEL: @test_mm512_reduce_add_epi64(
8-
// CHECK: call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %{{.*}})
10+
// CHECK-LABEL: test_mm512_reduce_add_epi64
11+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %{{.*}})
912
return _mm512_reduce_add_epi64(__W);
1013
}
1114
TEST_CONSTEXPR(_mm512_reduce_add_epi64((__m512i)(__v8di){-4, -3, -2, -1, 0, 1, 2, 3}) == -4);
1215

1316
long long test_mm512_reduce_mul_epi64(__m512i __W){
14-
// CHECK-LABEL: @test_mm512_reduce_mul_epi64(
15-
// CHECK: call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %{{.*}})
17+
// CHECK-LABEL: test_mm512_reduce_mul_epi64
18+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %{{.*}})
1619
return _mm512_reduce_mul_epi64(__W);
1720
}
1821
TEST_CONSTEXPR(_mm512_reduce_mul_epi64((__m512i)(__v8di){1, 2, 3, 4, 5, 6, 7, 8}) == 40320);
1922

2023
long long test_mm512_reduce_or_epi64(__m512i __W){
21-
// CHECK-LABEL: @test_mm512_reduce_or_epi64(
22-
// CHECK: call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %{{.*}})
24+
// CHECK-LABEL: test_mm512_reduce_or_epi64
25+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %{{.*}})
2326
return _mm512_reduce_or_epi64(__W);
2427
}
2528
TEST_CONSTEXPR(_mm512_reduce_or_epi64((__m512i)(__v8di){0x100, 0x200, 0x400, 0x800, 0, 0, 0, 0}) == 0xF00);
2629

2730
long long test_mm512_reduce_and_epi64(__m512i __W){
28-
// CHECK-LABEL: @test_mm512_reduce_and_epi64(
29-
// CHECK: call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %{{.*}})
31+
// CHECK-LABEL: test_mm512_reduce_and_epi64
32+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %{{.*}})
3033
return _mm512_reduce_and_epi64(__W);
3134
}
3235
TEST_CONSTEXPR(_mm512_reduce_and_epi64((__m512i)(__v8di){0xFFFF, 0xFF00, 0x00FF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFF00, 0x00FF}) == 0x0000);
3336

3437
long long test_mm512_mask_reduce_add_epi64(__mmask8 __M, __m512i __W){
35-
// CHECK-LABEL: @test_mm512_mask_reduce_add_epi64(
38+
// CHECK-LABEL: test_mm512_mask_reduce_add_epi64
3639
// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
37-
// CHECK: call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %{{.*}})
40+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %{{.*}})
3841
return _mm512_mask_reduce_add_epi64(__M, __W);
3942
}
4043

4144
long long test_mm512_mask_reduce_mul_epi64(__mmask8 __M, __m512i __W){
42-
// CHECK-LABEL: @test_mm512_mask_reduce_mul_epi64(
45+
// CHECK-LABEL: test_mm512_mask_reduce_mul_epi64
4346
// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
44-
// CHECK: call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %{{.*}})
47+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %{{.*}})
4548
return _mm512_mask_reduce_mul_epi64(__M, __W);
4649
}
4750

4851
long long test_mm512_mask_reduce_and_epi64(__mmask8 __M, __m512i __W){
49-
// CHECK-LABEL: @test_mm512_mask_reduce_and_epi64(
52+
// CHECK-LABEL: test_mm512_mask_reduce_and_epi64
5053
// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
51-
// CHECK: call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %{{.*}})
54+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %{{.*}})
5255
return _mm512_mask_reduce_and_epi64(__M, __W);
5356
}
5457

5558
long long test_mm512_mask_reduce_or_epi64(__mmask8 __M, __m512i __W){
56-
// CHECK-LABEL: @test_mm512_mask_reduce_or_epi64(
59+
// CHECK-LABEL: test_mm512_mask_reduce_or_epi64
5760
// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
58-
// CHECK: call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %{{.*}})
61+
// CHECK: call {{.*}}i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %{{.*}})
5962
return _mm512_mask_reduce_or_epi64(__M, __W);
6063
}
6164

6265
int test_mm512_reduce_add_epi32(__m512i __W){
63-
// CHECK-LABEL: @test_mm512_reduce_add_epi32(
64-
// CHECK: call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %{{.*}})
66+
// CHECK-LABEL: test_mm512_reduce_add_epi32
67+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %{{.*}})
6568
return _mm512_reduce_add_epi32(__W);
6669
}
6770
TEST_CONSTEXPR(_mm512_reduce_add_epi32((__m512i)(__v16si){-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}) == -8);
6871

6972
int test_mm512_reduce_mul_epi32(__m512i __W){
70-
// CHECK-LABEL: @test_mm512_reduce_mul_epi32(
71-
// CHECK: call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %{{.*}})
73+
// CHECK-LABEL: test_mm512_reduce_mul_epi32
74+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %{{.*}})
7275
return _mm512_reduce_mul_epi32(__W);
7376
}
7477
TEST_CONSTEXPR(_mm512_reduce_mul_epi32((__m512i)(__v16si){1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 3, 1, 1, -3, 1, 1}) == -36);
7578

7679
int test_mm512_reduce_or_epi32(__m512i __W){
77-
// CHECK: call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %{{.*}})
80+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %{{.*}})
7881
return _mm512_reduce_or_epi32(__W);
7982
}
8083
TEST_CONSTEXPR(_mm512_reduce_or_epi32((__m512i)(__v16si){0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0, 0, 0, 0, 0, 0, 0, 0}) == 0xFF);
8184

8285
int test_mm512_reduce_and_epi32(__m512i __W){
83-
// CHECK-LABEL: @test_mm512_reduce_and_epi32(
84-
// CHECK: call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %{{.*}})
86+
// CHECK-LABEL: test_mm512_reduce_and_epi32
87+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %{{.*}})
8588
return _mm512_reduce_and_epi32(__W);
8689
}
8790
TEST_CONSTEXPR(_mm512_reduce_and_epi32((__m512i)(__v16si){0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0x0F, 0x0F}) == 0x00);
8891

8992
int test_mm512_mask_reduce_add_epi32(__mmask16 __M, __m512i __W){
90-
// CHECK-LABEL: @test_mm512_mask_reduce_add_epi32(
93+
// CHECK-LABEL: test_mm512_mask_reduce_add_epi32
9194
// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
92-
// CHECK: call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %{{.*}})
95+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %{{.*}})
9396
return _mm512_mask_reduce_add_epi32(__M, __W);
9497
}
9598

9699
int test_mm512_mask_reduce_mul_epi32(__mmask16 __M, __m512i __W){
97-
// CHECK-LABEL: @test_mm512_mask_reduce_mul_epi32(
100+
// CHECK-LABEL: test_mm512_mask_reduce_mul_epi32
98101
// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
99-
// CHECK: call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %{{.*}})
102+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %{{.*}})
100103
return _mm512_mask_reduce_mul_epi32(__M, __W);
101104
}
102105

103106
int test_mm512_mask_reduce_and_epi32(__mmask16 __M, __m512i __W){
104-
// CHECK-LABEL: @test_mm512_mask_reduce_and_epi32(
107+
// CHECK-LABEL: test_mm512_mask_reduce_and_epi32
105108
// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
106-
// CHECK: call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %{{.*}})
109+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %{{.*}})
107110
return _mm512_mask_reduce_and_epi32(__M, __W);
108111
}
109112

110113
int test_mm512_mask_reduce_or_epi32(__mmask16 __M, __m512i __W){
111-
// CHECK-LABEL: @test_mm512_mask_reduce_or_epi32(
114+
// CHECK-LABEL: test_mm512_mask_reduce_or_epi32
112115
// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
113-
// CHECK: call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %{{.*}})
116+
// CHECK: call {{.*}}i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %{{.*}})
114117
return _mm512_mask_reduce_or_epi32(__M, __W);
115118
}
116119

117120
double test_mm512_reduce_add_pd(__m512d __W, double ExtraAddOp){
118-
// CHECK-LABEL: @test_mm512_reduce_add_pd(
121+
// CHECK-LABEL: test_mm512_reduce_add_pd
119122
// CHECK-NOT: reassoc
120-
// CHECK: call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %{{.*}})
123+
// CHECK: call reassoc {{.*}}double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %{{.*}})
121124
// CHECK-NOT: reassoc
122125
return _mm512_reduce_add_pd(__W) + ExtraAddOp;
123126
}
124127

125128
double test_mm512_reduce_mul_pd(__m512d __W, double ExtraMulOp){
126-
// CHECK-LABEL: @test_mm512_reduce_mul_pd(
129+
// CHECK-LABEL: test_mm512_reduce_mul_pd
127130
// CHECK-NOT: reassoc
128-
// CHECK: call reassoc double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> %{{.*}})
131+
// CHECK: call reassoc {{.*}}double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> %{{.*}})
129132
// CHECK-NOT: reassoc
130133
return _mm512_reduce_mul_pd(__W) * ExtraMulOp;
131134
}
132135

133136
float test_mm512_reduce_add_ps(__m512 __W){
134-
// CHECK-LABEL: @test_mm512_reduce_add_ps(
135-
// CHECK: call reassoc float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %{{.*}})
137+
// CHECK-LABEL: test_mm512_reduce_add_ps
138+
// CHECK: call reassoc {{.*}}float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %{{.*}})
136139
return _mm512_reduce_add_ps(__W);
137140
}
138141

139142
float test_mm512_reduce_mul_ps(__m512 __W){
140-
// CHECK-LABEL: @test_mm512_reduce_mul_ps(
141-
// CHECK: call reassoc float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> %{{.*}})
143+
// CHECK-LABEL: test_mm512_reduce_mul_ps
144+
// CHECK: call reassoc {{.*}}float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> %{{.*}})
142145
return _mm512_reduce_mul_ps(__W);
143146
}
144147

145148
double test_mm512_mask_reduce_add_pd(__mmask8 __M, __m512d __W){
146-
// CHECK-LABEL: @test_mm512_mask_reduce_add_pd(
149+
// CHECK-LABEL: test_mm512_mask_reduce_add_pd
147150
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
148-
// CHECK: call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %{{.*}})
151+
// CHECK: call reassoc {{.*}}double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %{{.*}})
149152
return _mm512_mask_reduce_add_pd(__M, __W);
150153
}
151154

152155
double test_mm512_mask_reduce_mul_pd(__mmask8 __M, __m512d __W){
153-
// CHECK-LABEL: @test_mm512_mask_reduce_mul_pd(
156+
// CHECK-LABEL: test_mm512_mask_reduce_mul_pd
154157
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
155-
// CHECK: call reassoc double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> %{{.*}})
158+
// CHECK: call reassoc {{.*}}double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> %{{.*}})
156159
return _mm512_mask_reduce_mul_pd(__M, __W);
157160
}
158161

159162
float test_mm512_mask_reduce_add_ps(__mmask16 __M, __m512 __W){
160-
// CHECK-LABEL: @test_mm512_mask_reduce_add_ps(
163+
// CHECK-LABEL: test_mm512_mask_reduce_add_ps
161164
// CHECK: select <16 x i1> %{{.*}}, <16 x float> {{.*}}, <16 x float> {{.*}}
162-
// CHECK: call reassoc float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %{{.*}})
165+
// CHECK: call reassoc {{.*}}float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %{{.*}})
163166
return _mm512_mask_reduce_add_ps(__M, __W);
164167
}
165168

166169
float test_mm512_mask_reduce_mul_ps(__mmask16 __M, __m512 __W){
167-
// CHECK-LABEL: @test_mm512_mask_reduce_mul_ps(
170+
// CHECK-LABEL: test_mm512_mask_reduce_mul_ps
168171
// CHECK: select <16 x i1> %{{.*}}, <16 x float> {{.*}}, <16 x float> %{{.*}}
169-
// CHECK: call reassoc float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> %{{.*}})
172+
// CHECK: call reassoc {{.*}}float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> %{{.*}})
170173
return _mm512_mask_reduce_mul_ps(__M, __W);
171174
}

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