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Added MIR test & some comments
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2956,9 +2956,11 @@ AArch64TargetLowering::EmitCheckMatchingVL(MachineInstr &MI,
29562956
Register RegSVL = MRI.createVirtualRegister(RC);
29572957
Register RegCheck = MRI.createVirtualRegister(RC);
29582958

2959+
// Read VL and Streaming VL
29592960
BuildMI(*MBB, MI, DL, TII->get(AArch64::RDVLI_XI), RegVL).addImm(1);
29602961
BuildMI(*MBB, MI, DL, TII->get(AArch64::RDSVLI_XI), RegSVL).addImm(1);
29612962

2963+
// Compare vector lengths
29622964
BuildMI(*MBB, MI, DL, TII->get(AArch64::SUBXrr), RegCheck)
29632965
.addReg(RegVL)
29642966
.addReg(RegSVL);
@@ -2968,6 +2970,7 @@ AArch64TargetLowering::EmitCheckMatchingVL(MachineInstr &MI,
29682970
MF->insert(It, TrapBB);
29692971
MF->insert(It, PassBB);
29702972

2973+
// Continue if vector lengths match
29712974
BuildMI(*MBB, MI, DL, TII->get(AArch64::CBZX))
29722975
.addReg(RegCheck)
29732976
.addMBB(PassBB);
@@ -2977,6 +2980,7 @@ AArch64TargetLowering::EmitCheckMatchingVL(MachineInstr &MI,
29772980
std::next(MachineBasicBlock::iterator(MI)), MBB->end());
29782981
PassBB->transferSuccessorsAndUpdatePHIs(MBB);
29792982

2983+
// Trap if vector lengths mismatch
29802984
BuildMI(TrapBB, DL, TII->get(AArch64::BRK)).addImm(1);
29812985

29822986
MBB->addSuccessor(TrapBB);

‎llvm/test/CodeGen/AArch64/sme-streaming-checkvl-mir.ll‎

Lines changed: 209 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,209 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme,+sme2p1 -stop-before=finalize-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BEFORE-ISEL
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme,+sme2p1 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-AFTER-ISEL
4+
5+
target triple = "aarch64-unknown-linux-gnu"
6+
7+
declare void @bar_enabled(<vscale x 4 x i32>) #0
8+
declare void @bar(<vscale x 4 x i32>)
9+
declare <vscale x 4 x i32> @bar_retv_enabled() #0
10+
declare <vscale x 4 x i32> @bar_retv()
11+
12+
; Non-streaming -> calls streaming callee
13+
define void @foo_non_streaming_pass_arg(ptr %arg) {
14+
; CHECK-BEFORE-ISEL-LABEL: name: foo_non_streaming_pass_arg
15+
; CHECK-BEFORE-ISEL: bb.0.entry:
16+
; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
17+
; CHECK-BEFORE-ISEL-NEXT: {{ $}}
18+
; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
19+
; CHECK-BEFORE-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
20+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
21+
; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
22+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
23+
; CHECK-BEFORE-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
24+
; CHECK-BEFORE-ISEL-NEXT: BL @bar_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
25+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
26+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
27+
; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
28+
;
29+
; CHECK-AFTER-ISEL-LABEL: name: foo_non_streaming_pass_arg
30+
; CHECK-AFTER-ISEL: bb.0.entry:
31+
; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
32+
; CHECK-AFTER-ISEL-NEXT: liveins: $x0
33+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
34+
; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
35+
; CHECK-AFTER-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
36+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
37+
; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
38+
; CHECK-AFTER-ISEL-NEXT: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg
39+
; CHECK-AFTER-ISEL-NEXT: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr [[RDVLI_XI]], [[RDSVLI_XI]]
40+
; CHECK-AFTER-ISEL-NEXT: CBZX [[SUBXrr]], %bb.2
41+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
42+
; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
43+
; CHECK-AFTER-ISEL-NEXT: successors:
44+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
45+
; CHECK-AFTER-ISEL-NEXT: BRK 1
46+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
47+
; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
48+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
49+
; CHECK-AFTER-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
50+
; CHECK-AFTER-ISEL-NEXT: BL @bar_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
51+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
52+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
53+
; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
54+
entry:
55+
%v = load <vscale x 4 x i32>, ptr %arg, align 16
56+
tail call void @bar_enabled(<vscale x 4 x i32> %v) #0
57+
ret void
58+
}
59+
60+
; Streaming -> calls non-streaming callee
61+
define void @foo_streaming_pass_arg(ptr %arg) #0 {
62+
; CHECK-BEFORE-ISEL-LABEL: name: foo_streaming_pass_arg
63+
; CHECK-BEFORE-ISEL: bb.0.entry:
64+
; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
65+
; CHECK-BEFORE-ISEL-NEXT: {{ $}}
66+
; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
67+
; CHECK-BEFORE-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
68+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
69+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
70+
; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
71+
; CHECK-BEFORE-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
72+
; CHECK-BEFORE-ISEL-NEXT: BL @bar, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
73+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
74+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
75+
; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
76+
;
77+
; CHECK-AFTER-ISEL-LABEL: name: foo_streaming_pass_arg
78+
; CHECK-AFTER-ISEL: bb.0.entry:
79+
; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
80+
; CHECK-AFTER-ISEL-NEXT: liveins: $x0
81+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
82+
; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
83+
; CHECK-AFTER-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
84+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
85+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
86+
; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
87+
; CHECK-AFTER-ISEL-NEXT: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg
88+
; CHECK-AFTER-ISEL-NEXT: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr [[RDVLI_XI]], [[RDSVLI_XI]]
89+
; CHECK-AFTER-ISEL-NEXT: CBZX [[SUBXrr]], %bb.2
90+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
91+
; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
92+
; CHECK-AFTER-ISEL-NEXT: successors:
93+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
94+
; CHECK-AFTER-ISEL-NEXT: BRK 1
95+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
96+
; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
97+
; CHECK-AFTER-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
98+
; CHECK-AFTER-ISEL-NEXT: BL @bar, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
99+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
100+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
101+
; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
102+
entry:
103+
%v = load <vscale x 4 x i32>, ptr %arg, align 16
104+
tail call void @bar(<vscale x 4 x i32> %v)
105+
ret void
106+
}
107+
108+
; Non-streaming -> returns SVE value from streaming callee
109+
define void @foo_non_streaming_retval(ptr %ptr) {
110+
; CHECK-BEFORE-ISEL-LABEL: name: foo_non_streaming_retval
111+
; CHECK-BEFORE-ISEL: bb.0.entry:
112+
; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
113+
; CHECK-BEFORE-ISEL-NEXT: {{ $}}
114+
; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
115+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
116+
; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
117+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
118+
; CHECK-BEFORE-ISEL-NEXT: BL @bar_retv_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
119+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
120+
; CHECK-BEFORE-ISEL-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
121+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
122+
; CHECK-BEFORE-ISEL-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
123+
; CHECK-BEFORE-ISEL-NEXT: STR_ZXI [[COPY2]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
124+
; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
125+
;
126+
; CHECK-AFTER-ISEL-LABEL: name: foo_non_streaming_retval
127+
; CHECK-AFTER-ISEL: bb.0.entry:
128+
; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
129+
; CHECK-AFTER-ISEL-NEXT: liveins: $x0
130+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
131+
; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
132+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
133+
; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
134+
; CHECK-AFTER-ISEL-NEXT: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg
135+
; CHECK-AFTER-ISEL-NEXT: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr [[RDVLI_XI]], [[RDSVLI_XI]]
136+
; CHECK-AFTER-ISEL-NEXT: CBZX [[SUBXrr]], %bb.2
137+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
138+
; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
139+
; CHECK-AFTER-ISEL-NEXT: successors:
140+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
141+
; CHECK-AFTER-ISEL-NEXT: BRK 1
142+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
143+
; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
144+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
145+
; CHECK-AFTER-ISEL-NEXT: BL @bar_retv_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
146+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
147+
; CHECK-AFTER-ISEL-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
148+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
149+
; CHECK-AFTER-ISEL-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
150+
; CHECK-AFTER-ISEL-NEXT: STR_ZXI [[COPY2]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
151+
; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
152+
entry:
153+
%v = tail call <vscale x 4 x i32> @bar_retv_enabled() #0
154+
store <vscale x 4 x i32> %v, ptr %ptr, align 16
155+
ret void
156+
}
157+
158+
; Streaming -> returns SVE value from non-streaming callee
159+
define void @foo_streaming_retval(ptr %ptr) #0 {
160+
; CHECK-BEFORE-ISEL-LABEL: name: foo_streaming_retval
161+
; CHECK-BEFORE-ISEL: bb.0.entry:
162+
; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
163+
; CHECK-BEFORE-ISEL-NEXT: {{ $}}
164+
; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
165+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
166+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
167+
; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
168+
; CHECK-BEFORE-ISEL-NEXT: BL @bar_retv, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
169+
; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
170+
; CHECK-BEFORE-ISEL-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
171+
; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
172+
; CHECK-BEFORE-ISEL-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
173+
; CHECK-BEFORE-ISEL-NEXT: STR_ZXI [[COPY2]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
174+
; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
175+
;
176+
; CHECK-AFTER-ISEL-LABEL: name: foo_streaming_retval
177+
; CHECK-AFTER-ISEL: bb.0.entry:
178+
; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
179+
; CHECK-AFTER-ISEL-NEXT: liveins: $x0
180+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
181+
; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
182+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
183+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
184+
; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
185+
; CHECK-AFTER-ISEL-NEXT: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg
186+
; CHECK-AFTER-ISEL-NEXT: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr [[RDVLI_XI]], [[RDSVLI_XI]]
187+
; CHECK-AFTER-ISEL-NEXT: CBZX [[SUBXrr]], %bb.2
188+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
189+
; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
190+
; CHECK-AFTER-ISEL-NEXT: successors:
191+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
192+
; CHECK-AFTER-ISEL-NEXT: BRK 1
193+
; CHECK-AFTER-ISEL-NEXT: {{ $}}
194+
; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
195+
; CHECK-AFTER-ISEL-NEXT: BL @bar_retv, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
196+
; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
197+
; CHECK-AFTER-ISEL-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
198+
; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
199+
; CHECK-AFTER-ISEL-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
200+
; CHECK-AFTER-ISEL-NEXT: STR_ZXI [[COPY2]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
201+
; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
202+
entry:
203+
%v = tail call <vscale x 4 x i32> @bar_retv()
204+
store <vscale x 4 x i32> %v, ptr %ptr, align 16
205+
ret void
206+
}
207+
208+
attributes #0 = { "aarch64_pstate_sm_enabled" }
209+
attributes #1 = { "aarch64_pstate_sm_compatible" }

‎llvm/test/CodeGen/AArch64/sme-streaming-checkvl.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme,+sme2p1 < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme,+sme2p1 -verify-machineinstrs < %s | FileCheck %s
33

44
target triple = "aarch64-unknown-linux-gnu"
55

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