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[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
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‎llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d \
33
; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64ID
4+
; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64 \
5+
; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64IDINX
46

57
; This file exhaustively checks double<->i32 conversions. In general,
68
; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
@@ -12,6 +14,11 @@ define i32 @aext_fptosi(double %a) nounwind strictfp {
1214
; RV64ID: # %bb.0:
1315
; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
1416
; RV64ID-NEXT: ret
17+
;
18+
; RV64IDINX-LABEL: aext_fptosi:
19+
; RV64IDINX: # %bb.0:
20+
; RV64IDINX-NEXT: fcvt.w.d a0, a0, rtz
21+
; RV64IDINX-NEXT: ret
1522
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
1623
ret i32 %1
1724
}
@@ -22,6 +29,11 @@ define signext i32 @sext_fptosi(double %a) nounwind strictfp {
2229
; RV64ID: # %bb.0:
2330
; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
2431
; RV64ID-NEXT: ret
32+
;
33+
; RV64IDINX-LABEL: sext_fptosi:
34+
; RV64IDINX: # %bb.0:
35+
; RV64IDINX-NEXT: fcvt.w.d a0, a0, rtz
36+
; RV64IDINX-NEXT: ret
2537
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
2638
ret i32 %1
2739
}
@@ -33,6 +45,13 @@ define zeroext i32 @zext_fptosi(double %a) nounwind strictfp {
3345
; RV64ID-NEXT: slli a0, a0, 32
3446
; RV64ID-NEXT: srli a0, a0, 32
3547
; RV64ID-NEXT: ret
48+
;
49+
; RV64IDINX-LABEL: zext_fptosi:
50+
; RV64IDINX: # %bb.0:
51+
; RV64IDINX-NEXT: fcvt.w.d a0, a0, rtz
52+
; RV64IDINX-NEXT: slli a0, a0, 32
53+
; RV64IDINX-NEXT: srli a0, a0, 32
54+
; RV64IDINX-NEXT: ret
3655
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
3756
ret i32 %1
3857
}
@@ -42,6 +61,11 @@ define i32 @aext_fptoui(double %a) nounwind strictfp {
4261
; RV64ID: # %bb.0:
4362
; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
4463
; RV64ID-NEXT: ret
64+
;
65+
; RV64IDINX-LABEL: aext_fptoui:
66+
; RV64IDINX: # %bb.0:
67+
; RV64IDINX-NEXT: fcvt.wu.d a0, a0, rtz
68+
; RV64IDINX-NEXT: ret
4569
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
4670
ret i32 %1
4771
}
@@ -52,6 +76,11 @@ define signext i32 @sext_fptoui(double %a) nounwind strictfp {
5276
; RV64ID: # %bb.0:
5377
; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
5478
; RV64ID-NEXT: ret
79+
;
80+
; RV64IDINX-LABEL: sext_fptoui:
81+
; RV64IDINX: # %bb.0:
82+
; RV64IDINX-NEXT: fcvt.wu.d a0, a0, rtz
83+
; RV64IDINX-NEXT: ret
5584
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
5685
ret i32 %1
5786
}
@@ -61,6 +90,11 @@ define zeroext i32 @zext_fptoui(double %a) nounwind strictfp {
6190
; RV64ID: # %bb.0:
6291
; RV64ID-NEXT: fcvt.lu.d a0, fa0, rtz
6392
; RV64ID-NEXT: ret
93+
;
94+
; RV64IDINX-LABEL: zext_fptoui:
95+
; RV64IDINX: # %bb.0:
96+
; RV64IDINX-NEXT: fcvt.lu.d a0, a0, rtz
97+
; RV64IDINX-NEXT: ret
6498
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
6599
ret i32 %1
66100
}
@@ -70,6 +104,11 @@ define double @uitofp_aext_i32_to_f64(i32 %a) nounwind strictfp {
70104
; RV64ID: # %bb.0:
71105
; RV64ID-NEXT: fcvt.d.wu fa0, a0
72106
; RV64ID-NEXT: ret
107+
;
108+
; RV64IDINX-LABEL: uitofp_aext_i32_to_f64:
109+
; RV64IDINX: # %bb.0:
110+
; RV64IDINX-NEXT: fcvt.d.wu a0, a0
111+
; RV64IDINX-NEXT: ret
73112
%1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
74113
ret double %1
75114
}
@@ -80,6 +119,11 @@ define double @uitofp_sext_i32_to_f64(i32 signext %a) nounwind strictfp {
80119
; RV64ID: # %bb.0:
81120
; RV64ID-NEXT: fcvt.d.wu fa0, a0
82121
; RV64ID-NEXT: ret
122+
;
123+
; RV64IDINX-LABEL: uitofp_sext_i32_to_f64:
124+
; RV64IDINX: # %bb.0:
125+
; RV64IDINX-NEXT: fcvt.d.wu a0, a0
126+
; RV64IDINX-NEXT: ret
83127
%1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
84128
ret double %1
85129
}
@@ -89,6 +133,11 @@ define double @uitofp_zext_i32_to_f64(i32 zeroext %a) nounwind strictfp {
89133
; RV64ID: # %bb.0:
90134
; RV64ID-NEXT: fcvt.d.wu fa0, a0
91135
; RV64ID-NEXT: ret
136+
;
137+
; RV64IDINX-LABEL: uitofp_zext_i32_to_f64:
138+
; RV64IDINX: # %bb.0:
139+
; RV64IDINX-NEXT: fcvt.d.wu a0, a0
140+
; RV64IDINX-NEXT: ret
92141
%1 = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
93142
ret double %1
94143
}
@@ -98,6 +147,11 @@ define double @sitofp_aext_i32_to_f64(i32 %a) nounwind strictfp {
98147
; RV64ID: # %bb.0:
99148
; RV64ID-NEXT: fcvt.d.w fa0, a0
100149
; RV64ID-NEXT: ret
150+
;
151+
; RV64IDINX-LABEL: sitofp_aext_i32_to_f64:
152+
; RV64IDINX: # %bb.0:
153+
; RV64IDINX-NEXT: fcvt.d.w a0, a0
154+
; RV64IDINX-NEXT: ret
101155
%1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
102156
ret double %1
103157
}
@@ -108,6 +162,11 @@ define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind strictfp {
108162
; RV64ID: # %bb.0:
109163
; RV64ID-NEXT: fcvt.d.w fa0, a0
110164
; RV64ID-NEXT: ret
165+
;
166+
; RV64IDINX-LABEL: sitofp_sext_i32_to_f64:
167+
; RV64IDINX: # %bb.0:
168+
; RV64IDINX-NEXT: fcvt.d.w a0, a0
169+
; RV64IDINX-NEXT: ret
111170
%1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
112171
ret double %1
113172
}
@@ -117,6 +176,11 @@ define double @sitofp_zext_i32_to_f64(i32 zeroext %a) nounwind strictfp {
117176
; RV64ID: # %bb.0:
118177
; RV64ID-NEXT: fcvt.d.w fa0, a0
119178
; RV64ID-NEXT: ret
179+
;
180+
; RV64IDINX-LABEL: sitofp_zext_i32_to_f64:
181+
; RV64IDINX: # %bb.0:
182+
; RV64IDINX-NEXT: fcvt.d.w a0, a0
183+
; RV64IDINX-NEXT: ret
120184
%1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
121185
ret double %1
122186
}

‎llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
33
; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IF
4+
; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi=lp64 -verify-machineinstrs < %s \
5+
; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64IFINX
46

57
; This file exhaustively checks float<->i32 conversions. In general,
68
; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
@@ -12,6 +14,11 @@ define i32 @aext_fptosi(float %a) nounwind strictfp {
1214
; RV64IF: # %bb.0:
1315
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
1416
; RV64IF-NEXT: ret
17+
;
18+
; RV64IFINX-LABEL: aext_fptosi:
19+
; RV64IFINX: # %bb.0:
20+
; RV64IFINX-NEXT: fcvt.w.s a0, a0, rtz
21+
; RV64IFINX-NEXT: ret
1522
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
1623
ret i32 %1
1724
}
@@ -22,6 +29,11 @@ define signext i32 @sext_fptosi(float %a) nounwind strictfp {
2229
; RV64IF: # %bb.0:
2330
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
2431
; RV64IF-NEXT: ret
32+
;
33+
; RV64IFINX-LABEL: sext_fptosi:
34+
; RV64IFINX: # %bb.0:
35+
; RV64IFINX-NEXT: fcvt.w.s a0, a0, rtz
36+
; RV64IFINX-NEXT: ret
2537
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
2638
ret i32 %1
2739
}
@@ -33,6 +45,13 @@ define zeroext i32 @zext_fptosi(float %a) nounwind strictfp {
3345
; RV64IF-NEXT: slli a0, a0, 32
3446
; RV64IF-NEXT: srli a0, a0, 32
3547
; RV64IF-NEXT: ret
48+
;
49+
; RV64IFINX-LABEL: zext_fptosi:
50+
; RV64IFINX: # %bb.0:
51+
; RV64IFINX-NEXT: fcvt.w.s a0, a0, rtz
52+
; RV64IFINX-NEXT: slli a0, a0, 32
53+
; RV64IFINX-NEXT: srli a0, a0, 32
54+
; RV64IFINX-NEXT: ret
3655
%1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
3756
ret i32 %1
3857
}
@@ -42,6 +61,11 @@ define i32 @aext_fptoui(float %a) nounwind strictfp {
4261
; RV64IF: # %bb.0:
4362
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
4463
; RV64IF-NEXT: ret
64+
;
65+
; RV64IFINX-LABEL: aext_fptoui:
66+
; RV64IFINX: # %bb.0:
67+
; RV64IFINX-NEXT: fcvt.wu.s a0, a0, rtz
68+
; RV64IFINX-NEXT: ret
4569
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
4670
ret i32 %1
4771
}
@@ -52,6 +76,11 @@ define signext i32 @sext_fptoui(float %a) nounwind strictfp {
5276
; RV64IF: # %bb.0:
5377
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
5478
; RV64IF-NEXT: ret
79+
;
80+
; RV64IFINX-LABEL: sext_fptoui:
81+
; RV64IFINX: # %bb.0:
82+
; RV64IFINX-NEXT: fcvt.wu.s a0, a0, rtz
83+
; RV64IFINX-NEXT: ret
5584
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
5685
ret i32 %1
5786
}
@@ -61,6 +90,11 @@ define zeroext i32 @zext_fptoui(float %a) nounwind strictfp {
6190
; RV64IF: # %bb.0:
6291
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
6392
; RV64IF-NEXT: ret
93+
;
94+
; RV64IFINX-LABEL: zext_fptoui:
95+
; RV64IFINX: # %bb.0:
96+
; RV64IFINX-NEXT: fcvt.lu.s a0, a0, rtz
97+
; RV64IFINX-NEXT: ret
6498
%1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
6599
ret i32 %1
66100
}
@@ -70,6 +104,11 @@ define float @uitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
70104
; RV64IF: # %bb.0:
71105
; RV64IF-NEXT: fcvt.s.wu fa0, a0
72106
; RV64IF-NEXT: ret
107+
;
108+
; RV64IFINX-LABEL: uitofp_aext_i32_to_f32:
109+
; RV64IFINX: # %bb.0:
110+
; RV64IFINX-NEXT: fcvt.s.wu a0, a0
111+
; RV64IFINX-NEXT: ret
73112
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
74113
ret float %1
75114
}
@@ -80,6 +119,11 @@ define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
80119
; RV64IF: # %bb.0:
81120
; RV64IF-NEXT: fcvt.s.wu fa0, a0
82121
; RV64IF-NEXT: ret
122+
;
123+
; RV64IFINX-LABEL: uitofp_sext_i32_to_f32:
124+
; RV64IFINX: # %bb.0:
125+
; RV64IFINX-NEXT: fcvt.s.wu a0, a0
126+
; RV64IFINX-NEXT: ret
83127
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
84128
ret float %1
85129
}
@@ -89,6 +133,11 @@ define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
89133
; RV64IF: # %bb.0:
90134
; RV64IF-NEXT: fcvt.s.wu fa0, a0
91135
; RV64IF-NEXT: ret
136+
;
137+
; RV64IFINX-LABEL: uitofp_zext_i32_to_f32:
138+
; RV64IFINX: # %bb.0:
139+
; RV64IFINX-NEXT: fcvt.s.wu a0, a0
140+
; RV64IFINX-NEXT: ret
92141
%1 = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
93142
ret float %1
94143
}
@@ -98,6 +147,11 @@ define float @sitofp_aext_i32_to_f32(i32 %a) nounwind strictfp {
98147
; RV64IF: # %bb.0:
99148
; RV64IF-NEXT: fcvt.s.w fa0, a0
100149
; RV64IF-NEXT: ret
150+
;
151+
; RV64IFINX-LABEL: sitofp_aext_i32_to_f32:
152+
; RV64IFINX: # %bb.0:
153+
; RV64IFINX-NEXT: fcvt.s.w a0, a0
154+
; RV64IFINX-NEXT: ret
101155
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
102156
ret float %1
103157
}
@@ -108,6 +162,11 @@ define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind strictfp {
108162
; RV64IF: # %bb.0:
109163
; RV64IF-NEXT: fcvt.s.w fa0, a0
110164
; RV64IF-NEXT: ret
165+
;
166+
; RV64IFINX-LABEL: sitofp_sext_i32_to_f32:
167+
; RV64IFINX: # %bb.0:
168+
; RV64IFINX-NEXT: fcvt.s.w a0, a0
169+
; RV64IFINX-NEXT: ret
111170
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
112171
ret float %1
113172
}
@@ -117,6 +176,11 @@ define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind strictfp {
117176
; RV64IF: # %bb.0:
118177
; RV64IF-NEXT: fcvt.s.w fa0, a0
119178
; RV64IF-NEXT: ret
179+
;
180+
; RV64IFINX-LABEL: sitofp_zext_i32_to_f32:
181+
; RV64IFINX: # %bb.0:
182+
; RV64IFINX-NEXT: fcvt.s.w a0, a0
183+
; RV64IFINX-NEXT: ret
120184
%1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
121185
ret float %1
122186
}

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