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[ARM] Use MCRegister in more places. NFC
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6 files changed

+80
-80
lines changed

6 files changed

+80
-80
lines changed

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp‎

Lines changed: 46 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -759,7 +759,7 @@ class ARMAsmParser : public MCTargetAsmParser {
759759
bool hasMVE() const { return getSTI().hasFeature(ARM::HasMVEIntegerOps); }
760760

761761
// Return the low-subreg of a given Q register.
762-
unsigned getDRegFromQReg(unsigned QReg) const {
762+
MCRegister getDRegFromQReg(MCRegister QReg) const {
763763
return MRI->getSubReg(QReg, ARM::dsub_0);
764764
}
765765

@@ -862,12 +862,12 @@ class ARMOperand : public MCParsedAsmOperand {
862862
};
863863

864864
struct RegOp {
865-
unsigned RegNum;
865+
MCRegister RegNum;
866866
};
867867

868868
// A vector register list is a sequential list of 1 to 4 registers.
869869
struct VectorListOp {
870-
unsigned RegNum;
870+
MCRegister RegNum;
871871
unsigned Count;
872872
unsigned LaneIndex;
873873
bool isDoubleSpaced;
@@ -883,11 +883,11 @@ class ARMOperand : public MCParsedAsmOperand {
883883

884884
/// Combined record for all forms of ARM address expressions.
885885
struct MemoryOp {
886-
unsigned BaseRegNum;
886+
MCRegister BaseRegNum;
887887
// Offset is in OffsetReg or OffsetImm. If both are zero, no offset
888888
// was specified.
889889
const MCExpr *OffsetImm; // Offset immediate value
890-
unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
890+
MCRegister OffsetRegNum; // Offset register num, when OffsetImm == NULL
891891
ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
892892
unsigned ShiftImm; // shift for OffsetReg.
893893
unsigned Alignment; // 0 = no alignment specified
@@ -896,7 +896,7 @@ class ARMOperand : public MCParsedAsmOperand {
896896
};
897897

898898
struct PostIdxRegOp {
899-
unsigned RegNum;
899+
MCRegister RegNum;
900900
bool isAdd;
901901
ARM_AM::ShiftOpc ShiftTy;
902902
unsigned ShiftImm;
@@ -909,14 +909,14 @@ class ARMOperand : public MCParsedAsmOperand {
909909

910910
struct RegShiftedRegOp {
911911
ARM_AM::ShiftOpc ShiftTy;
912-
unsigned SrcReg;
913-
unsigned ShiftReg;
912+
MCRegister SrcReg;
913+
MCRegister ShiftReg;
914914
unsigned ShiftImm;
915915
};
916916

917917
struct RegShiftedImmOp {
918918
ARM_AM::ShiftOpc ShiftTy;
919-
unsigned SrcReg;
919+
MCRegister SrcReg;
920920
unsigned ShiftImm;
921921
};
922922

@@ -2547,9 +2547,9 @@ class ARMOperand : public MCParsedAsmOperand {
25472547
void addVPTPredROperands(MCInst &Inst, unsigned N) const {
25482548
assert(N == 4 && "Invalid number of operands!");
25492549
addVPTPredNOperands(Inst, N-1);
2550-
unsigned RegNum;
2550+
MCRegister RegNum;
25512551
if (getVPTPred() == ARMVCC::None) {
2552-
RegNum = 0;
2552+
RegNum = MCRegister();
25532553
} else {
25542554
unsigned NextOpIndex = Inst.getNumOperands();
25552555
auto &MCID = Parser->getInstrDesc(Inst.getOpcode());
@@ -3393,7 +3393,7 @@ class ARMOperand : public MCParsedAsmOperand {
33933393
else if (isDReg() && !Parser->hasMVE()) {
33943394
Inst.addOperand(MCOperand::createReg(Reg.RegNum));
33953395
} else if (isQReg() && !Parser->hasMVE()) {
3396-
auto DPair = Parser->getDRegFromQReg(Reg.RegNum);
3396+
MCRegister DPair = Parser->getDRegFromQReg(Reg.RegNum);
33973397
DPair = Parser->getMRI()->getMatchingSuperReg(
33983398
DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
33993399
Inst.addOperand(MCOperand::createReg(DPair));
@@ -3684,10 +3684,10 @@ class ARMOperand : public MCParsedAsmOperand {
36843684
return Op;
36853685
}
36863686

3687-
static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S,
3687+
static std::unique_ptr<ARMOperand> CreateCCOut(MCRegister Reg, SMLoc S,
36883688
ARMAsmParser &Parser) {
36893689
auto Op = std::make_unique<ARMOperand>(k_CCOut, Parser);
3690-
Op->Reg.RegNum = RegNum;
3690+
Op->Reg.RegNum = Reg;
36913691
Op->StartLoc = S;
36923692
Op->EndLoc = S;
36933693
return Op;
@@ -3703,19 +3703,19 @@ class ARMOperand : public MCParsedAsmOperand {
37033703
return Op;
37043704
}
37053705

3706-
static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3707-
SMLoc E, ARMAsmParser &Parser) {
3706+
static std::unique_ptr<ARMOperand> CreateReg(MCRegister Reg, SMLoc S, SMLoc E,
3707+
ARMAsmParser &Parser) {
37083708
auto Op = std::make_unique<ARMOperand>(k_Register, Parser);
3709-
Op->Reg.RegNum = RegNum;
3709+
Op->Reg.RegNum = Reg;
37103710
Op->StartLoc = S;
37113711
Op->EndLoc = E;
37123712
return Op;
37133713
}
37143714

37153715
static std::unique_ptr<ARMOperand>
3716-
CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3717-
unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E,
3718-
ARMAsmParser &Parser) {
3716+
CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg,
3717+
MCRegister ShiftReg, unsigned ShiftImm, SMLoc S,
3718+
SMLoc E, ARMAsmParser &Parser) {
37193719
auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister, Parser);
37203720
Op->RegShiftedReg.ShiftTy = ShTy;
37213721
Op->RegShiftedReg.SrcReg = SrcReg;
@@ -3727,7 +3727,7 @@ class ARMOperand : public MCParsedAsmOperand {
37273727
}
37283728

37293729
static std::unique_ptr<ARMOperand>
3730-
CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3730+
CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg,
37313731
unsigned ShiftImm, SMLoc S, SMLoc E,
37323732
ARMAsmParser &Parser) {
37333733
auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate, Parser);
@@ -3793,7 +3793,7 @@ class ARMOperand : public MCParsedAsmOperand {
37933793
}
37943794

37953795
static std::unique_ptr<ARMOperand>
3796-
CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3796+
CreateRegList(SmallVectorImpl<std::pair<unsigned, MCRegister>> &Regs,
37973797
SMLoc StartLoc, SMLoc EndLoc, ARMAsmParser &Parser) {
37983798
assert(Regs.size() > 0 && "RegList contains no registers?");
37993799
KindTy Kind = k_RegisterList;
@@ -3827,10 +3827,10 @@ class ARMOperand : public MCParsedAsmOperand {
38273827
}
38283828

38293829
static std::unique_ptr<ARMOperand>
3830-
CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3831-
SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3830+
CreateVectorList(MCRegister Reg, unsigned Count, bool isDoubleSpaced, SMLoc S,
3831+
SMLoc E, ARMAsmParser &Parser) {
38323832
auto Op = std::make_unique<ARMOperand>(k_VectorList, Parser);
3833-
Op->VectorList.RegNum = RegNum;
3833+
Op->VectorList.RegNum = Reg;
38343834
Op->VectorList.Count = Count;
38353835
Op->VectorList.isDoubleSpaced = isDoubleSpaced;
38363836
Op->StartLoc = S;
@@ -3839,10 +3839,10 @@ class ARMOperand : public MCParsedAsmOperand {
38393839
}
38403840

38413841
static std::unique_ptr<ARMOperand>
3842-
CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3842+
CreateVectorListAllLanes(MCRegister Reg, unsigned Count, bool isDoubleSpaced,
38433843
SMLoc S, SMLoc E, ARMAsmParser &Parser) {
38443844
auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes, Parser);
3845-
Op->VectorList.RegNum = RegNum;
3845+
Op->VectorList.RegNum = Reg;
38463846
Op->VectorList.Count = Count;
38473847
Op->VectorList.isDoubleSpaced = isDoubleSpaced;
38483848
Op->StartLoc = S;
@@ -3884,14 +3884,14 @@ class ARMOperand : public MCParsedAsmOperand {
38843884
}
38853885

38863886
static std::unique_ptr<ARMOperand>
3887-
CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
3887+
CreateMem(MCRegister BaseReg, const MCExpr *OffsetImm, MCRegister OffsetReg,
38883888
ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
38893889
bool isNegative, SMLoc S, SMLoc E, ARMAsmParser &Parser,
38903890
SMLoc AlignmentLoc = SMLoc()) {
38913891
auto Op = std::make_unique<ARMOperand>(k_Memory, Parser);
3892-
Op->Memory.BaseRegNum = BaseRegNum;
3892+
Op->Memory.BaseRegNum = BaseReg;
38933893
Op->Memory.OffsetImm = OffsetImm;
3894-
Op->Memory.OffsetRegNum = OffsetRegNum;
3894+
Op->Memory.OffsetRegNum = OffsetReg;
38953895
Op->Memory.ShiftType = ShiftType;
38963896
Op->Memory.ShiftImm = ShiftImm;
38973897
Op->Memory.Alignment = Alignment;
@@ -3903,10 +3903,10 @@ class ARMOperand : public MCParsedAsmOperand {
39033903
}
39043904

39053905
static std::unique_ptr<ARMOperand>
3906-
CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3906+
CreatePostIdxReg(MCRegister Reg, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
39073907
unsigned ShiftImm, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
39083908
auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister, Parser);
3909-
Op->PostIdxReg.RegNum = RegNum;
3909+
Op->PostIdxReg.RegNum = Reg;
39103910
Op->PostIdxReg.isAdd = isAdd;
39113911
Op->PostIdxReg.ShiftTy = ShiftTy;
39123912
Op->PostIdxReg.ShiftImm = ShiftImm;
@@ -4104,8 +4104,7 @@ void ARMOperand::print(raw_ostream &OS) const {
41044104
OS << "<register_list ";
41054105

41064106
const SmallVectorImpl<unsigned> &RegList = getRegList();
4107-
for (SmallVectorImpl<unsigned>::const_iterator
4108-
I = RegList.begin(), E = RegList.end(); I != E; ) {
4107+
for (auto I = RegList.begin(), E = RegList.end(); I != E;) {
41094108
OS << RegName(*I);
41104109
if (++I < E) OS << ", ";
41114110
}
@@ -4311,11 +4310,11 @@ int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
43114310
(ARMOperand *)Operands.pop_back_val().release());
43124311
if (!PrevOp->isReg())
43134312
return Error(PrevOp->getStartLoc(), "shift must be of a register");
4314-
int SrcReg = PrevOp->getReg();
4313+
MCRegister SrcReg = PrevOp->getReg();
43154314

43164315
SMLoc EndLoc;
43174316
int64_t Imm = 0;
4318-
int ShiftReg = 0;
4317+
MCRegister ShiftReg;
43194318
if (ShiftTy == ARM_AM::rrx) {
43204319
// RRX Doesn't have an explicit shift amount. The encoder expects
43214320
// the shift register to be the same as the source register. Seems odd,
@@ -4591,8 +4590,8 @@ static unsigned getNextRegister(unsigned Reg) {
45914590
// Insert an <Encoding, Register> pair in an ordered vector. Return true on
45924591
// success, or false, if duplicate encoding found.
45934592
static bool
4594-
insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4595-
unsigned Enc, unsigned Reg) {
4593+
insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, MCRegister>> &Regs,
4594+
unsigned Enc, MCRegister Reg) {
45964595
Regs.emplace_back(Enc, Reg);
45974596
for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
45984597
if (J->first == Enc) {
@@ -4626,7 +4625,7 @@ bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
46264625
// The reglist instructions have at most 16 registers, so reserve
46274626
// space for that many.
46284627
int EReg = 0;
4629-
SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
4628+
SmallVector<std::pair<unsigned, MCRegister>, 16> Registers;
46304629

46314630
// Allow Q regs and just interpret them as the two D sub-registers.
46324631
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
@@ -7409,9 +7408,9 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
74097408
const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
74107409
// Adjust only if Op1 is a GPR.
74117410
if (Op1.isReg() && MRC.contains(Op1.getReg())) {
7412-
unsigned Reg1 = Op1.getReg();
7411+
MCRegister Reg1 = Op1.getReg();
74137412
unsigned Rt = MRI->getEncodingValue(Reg1);
7414-
unsigned Reg2 = Op2.getReg();
7413+
MCRegister Reg2 = Op2.getReg();
74157414
unsigned Rt2 = MRI->getEncodingValue(Reg2);
74167415
// Rt2 must be Rt + 1.
74177416
if (Rt + 1 != Rt2)
@@ -7426,7 +7425,7 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
74267425
IsLoad ? "destination operands must start start at an even register"
74277426
: "source operands must start start at an even register");
74287427

7429-
unsigned NewReg = MRI->getMatchingSuperReg(
7428+
MCRegister NewReg = MRI->getMatchingSuperReg(
74307429
Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
74317430
Operands[Idx] = ARMOperand::CreateReg(NewReg, Op1.getStartLoc(),
74327431
Op2.getEndLoc(), *this);
@@ -7464,7 +7463,7 @@ static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
74647463
bool &containsReg) {
74657464
containsReg = false;
74667465
for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
7467-
unsigned OpReg = Inst.getOperand(i).getReg();
7466+
MCRegister OpReg = Inst.getOperand(i).getReg();
74687467
if (OpReg == Reg)
74697468
containsReg = true;
74707469
// Anything other than a low register isn't legal here.
@@ -7776,7 +7775,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
77767775
return true;
77777776
break;
77787777
case ARM::t2BXJ: {
7779-
const unsigned RmReg = Inst.getOperand(0).getReg();
7778+
const MCRegister RmReg = Inst.getOperand(0).getReg();
77807779
// Rm = SP is no longer unpredictable in v8-A
77817780
if (RmReg == ARM::SP && !hasV8Ops())
77827781
return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
@@ -8054,7 +8053,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
80548053
//
80558054
// Thumb LDM instructions are writeback iff the base register is not
80568055
// in the register list.
8057-
unsigned Rn = Inst.getOperand(0).getReg();
8056+
MCRegister Rn = Inst.getOperand(0).getReg();
80588057
bool HasWritebackToken =
80598058
(static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
80608059
.isToken() &&
@@ -8508,8 +8507,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
85088507
case ARM::t2SMLSLD:
85098508
case ARM::t2SMLSLDX:
85108509
case ARM::t2SMULL: {
8511-
unsigned RdHi = Inst.getOperand(0).getReg();
8512-
unsigned RdLo = Inst.getOperand(1).getReg();
8510+
MCRegister RdHi = Inst.getOperand(0).getReg();
8511+
MCRegister RdLo = Inst.getOperand(1).getReg();
85138512
if(RdHi == RdLo) {
85148513
return Error(Loc,
85158514
"unpredictable instruction, RdHi and RdLo must be different");

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1188,7 +1188,7 @@ uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
11881188
MCRegister CFARegister = ARM::SP;
11891189
int CFARegisterOffset = 0;
11901190
// Mark savable registers as initially unsaved
1191-
DenseMap<unsigned, int> RegOffsets;
1191+
DenseMap<MCRegister, int> RegOffsets;
11921192
int FloatRegCount = 0;
11931193
// Process each .cfi directive and build up compact unwind info.
11941194
for (const MCCFIInstruction &Inst : Instrs) {
@@ -1332,7 +1332,7 @@ uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
13321332
// Floating point registers must either be saved sequentially, or we defer to
13331333
// DWARF. No gaps allowed here so check that each saved d-register is
13341334
// precisely where it should be.
1335-
static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1335+
static MCPhysReg FPRCSRegs[] = {ARM::D8, ARM::D10, ARM::D12, ARM::D14};
13361336
for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
13371337
auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
13381338
if (Offset == RegOffsets.end()) {

‎llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,9 +157,9 @@ namespace ARM_ISB {
157157

158158
/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
159159
///
160-
static inline bool isARMLowRegister(unsigned Reg) {
160+
static inline bool isARMLowRegister(MCRegister Reg) {
161161
using namespace ARM;
162-
switch (Reg) {
162+
switch (Reg.id()) {
163163
case R0: case R1: case R2: case R3:
164164
case R4: case R5: case R6: case R7:
165165
return true;

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